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| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 56/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
6
FPGA Logic Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It
includes enhancements and innovations geared toward today’s high-speed systems on a single chip. Designed
with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce
logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhance-
ments and are offered in a variety of packages and speed grades.
The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge
of FPGA and ASIC designs. Modular hardware and software technologies enable System-on-Chip integration with
true plug-and-play design implementation.
The architecture consists of four basic elements: Programmable Logic Cells (PLCs), Programmable I/O cells
(PIOs), Embedded Block RAMs (EBRs), plus supporting system-level features. These elements are interconnected
with a rich routing fabric of both global and local wires. An array of PLCs is surrounded by common interface blocks
which provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these crit-
ical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core.
Each PLC contains a PFU, SLIC, local routing resources, and conguration RAM. Most of the FPGA logic is per-
formed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs
provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output
multiplexing, uplink and downlink functions, and other functions on two output signals.
Large blocks of 512 x 18 quad-port RAM complement the existing distributed PFU memory. The RAM blocks can
be used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the
MPI, PLLs, and the Embedded System Bus (ESB).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional Flip-Flop that
may be used independently or with arithmetic functions.
The PFU is organized in a twin-quad fashion; two sets of four LUTs and FFs that can be controlled independently.
Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. LUTs may
also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The
carry-out of either mode may be registered in the ninth FF for pipelining.
Each PFU may also be congured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The
FFs also have programmable clock polarity, clock enables, and local set/reset.
The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidi-
rectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional
INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU
outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for real-
world system performance.
Programmable I/O
The Series 4 PIO addresses the demand for the exibility to select I/Os that meet system interface requirements.
I/Os can be programmed in the same manner as in previous ORCA devices, with the additional new features which
allow the user the exibility to select new I/O types that support High-Speed Interfaces.
Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA
array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset,
and global set/reset. On the input side, each PIO contains a programmable latch/Flip-Flop which enables very fast
latching of data from any pad. The combination provides for very low setup requirements and zero hold times for
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