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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 63/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
66
Special-Purpose Pins
M[3:0]
I
During powerup and initialization, M0—M3 are used to select the conguration mode with their
values latched on the rising edge of INIT. During conguration, a pull-up is enabled.
I/O After conguration, these pins are user-programmable I/O.*
PLL_CK[0:7][TC]
I
Semi-dedicated PLL clock pins. During conguration they are 3-stated with a pull up.
I/O These pins are user-programmable I/O pins if not used by PLLs after conguration.
P[TBLR]CLK[1:0][TC]
I
Pins dedicated for the primary clock. Input pins on the middle of each side with differential pair-
ing.
I/O After conguration these pins are user programmable I/O, if not used for clock inputs.
TDI, TCK, TMS
I
If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If
boundary-scan is not selected, all boundary-scan functions are inhibited once conguration is
complete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during
conguration. Each pin has a pull-up enabled during conguration.
I/O After conguration, these pins are user-programmable I/O if boundary scan is not used.*
RDY/BUSY/RCLK
O
During conguration in asynchronous peripheral mode, RDY/RCLK indicates another byte can
be written to the FPGA. If a read operation is done when the device is selected, the same sta-
tus is also available on D7 in asynchronous peripheral mode.
During the master parallel conguration mode, RCLK is a read output signal to an external
memory. This output is not normally used.
I/O After conguration this pin is a user-programmable I/O pin.*
HDC
O
High During Conguration is output high until conguration is complete. It is used as a control
output, indicating that conguration is not complete.
I/O After conguration, this pin is a user-programmable I/O pin.*
LDC
O
Low During Conguration
is output low until conguration is complete. It is used as a control out-
put, indicating that conguration is not complete.
I/O After conguration, this pin is a user-programmable I/O pin.*
INIT
I/O INIT is a bidirectional signal before and during conguration. During conguration, a pull-up is
enabled, but an external pull-up resistor is recommended. As an active-low open-drain output,
INIT
is held low during power stabilization and internal clearing of memory. As an active-low
input, INIT holds the FPGA in the wait-state before the start of conguration.
After conguration, this pin is a user-programmable I/O pin.*
CS0, CS1
I
CS0
and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor con-
guration modes. The FPGA is selected when CS0 is low and CS1 is high. During congura-
tion, a pull-up is enabled.
I/O After conguration, if MPI is not used, these pins are user-programmable I/O pins.*
RD/MPI_STRB
I
RD
is used in the asynchronous peripheral conguration mode. A low on RD changes D[7:3]
into a status output. WR and RD should not be used simultaneously. If they are, the write strobe
overrides.
This pin is also used as the
MPI data transfer strobe. As a status indication, a high indicates
ready, and a low indicates busy.
WR/MPI_RW
I
WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the
FPGA.
In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write
transfer to the FPGA.
I/O After conguration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.*
PPC_A[14:31]
I
During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus
master utilizing the least-signicant bits of the PowerPC 32-bit address.
MPI_BURST
I
MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high
indicates that the current transfer is not a burst.
MPI_BDIP
I
MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that
the second beat in front of the current one is requested by the master. Negated before the burst
transfer ends to abort the burst data phase.
Symbol
I/O
Description
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