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| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 59/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
62
Figure 31. Receive Data Eye-Diagram Template (Differential)
Figure 31 provides a graphical characterization of the SERDES receiver input requirements. It provides guidance
on a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N
input skew tolerance. it is believed that incoming data patterns falling within the shaded region of the template will
be received without error (BER < 10E-12), over all specied operating conditions.
Data pattern eye-opening at the receive end of a link is considered the ultimate measure of received signal quality.
Almost all detrimental characteristics of transmit signal and the interconnection link design result in eye-closure.
This, combined with the eye-opening limitations of the line receiver, can provide a good indication of a link’s ability
to transfer data error-free.
Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital
links and of systems with high noise level environments. An interesting characteristic of the Clock and Data Recov-
ery (CDR) portion of the ORT82G5 SERDES receiver is its ability to lter incoming signal jitter that is below the
clock recovery PLL bandwidth (estimated to be about 3 MHz). For signals with high levels of low frequency jitter the
receiver can detect incoming data, error-free, with eye-openings signicantly less than that of Figure 31. . This phe-
nomenon has been observed in the laboratory.
Eye-diagram measurement and simulation are excellent tools of design. They are both highly recommended when
designing serial link interconnections and evaluating signal integrity.
Table 23. Receiver Specications
Parameter
Conditions
Min
Typ
Max
Unit
Input Data
Stream of Nontransitions
—
72
Bits
Eye Opening Interval
—
0.4
—
UIP-P
Eye Opening Voltage
—
200
—
mVP-P
0.4UI
TBD
1.2 V
UI
PRELIMINAR
Y
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