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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 26/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
32
The code violation signals will only be valid if the corresponding CV_SELxx = 1. (If 8b10bR=0, CV_SEL should
also be zero. The CV_xx_OR signals are obtained by ORing four code violation signals from the 1:4 DEMUX block.
These are primarily indicators of received signal quality since a single code violation will not force a loss of sync
(LOS) state in the word alignment state machines. Since these signals come from the DEMUX block, if multi-chan-
nel alignment is enabled, the code violation signals correspond to data that must still be multi-channel aligned.
Hence these signals provide advance notication of detected violations in data that will appear at the core/FPGA
interface several clock cycles later. The exact number of clock cycles that the data is delayed depends on the skew
between the incoming data for the different channels.
The
SYNC2_[A1,A2,B1,B2]_OOS,
SYNC4_[A:B]_OOS,and
SYNC8_OOS
signals
can
be
used
with
CH248_SYNC_xx to determine if the desired multi-channel alignment was successful. If, when CH248_SYNC_xx
goes high the corresponding OOS signal remains low, the data being transferred across the core/FPGA interface is
correctly aligned between channels. Note that only the signals corresponding to the selected alignment mode will
be meaningful.
Transceiver FPGA/Embedded Core Signals
Table 9 summarizes the interface signals between the FPGA logic and the core. In the table, an input refers to a
signal owing into the embedded core and an output refers to a signal owing out of the embedded core.
Table 8. Denition of the Status Bits of MRWDxx that Vary for Different Channels
Channel
Index
Bit Index
Name
Description
all
39
CH248_SYNCxx
Multi-channel alignment attempt complete if 1
AA
29
CV_AA_OR
Code violation in one or more of the received 10-bit groups for channel AB
AA
19
SYNC2_A1_OOS
Dual channel synchronization of channels AA and AB not successful if 1
AB
29
CV_AB_OR
Code violation in one or more of the received 10-bit groups for channel AB
AB
19
SYNC4_A_OOS
Quad channel synchronization of SERDES quad A not successful if 1
AC
29
CV_AC_OR
Code violation in one or more of the received 10-bit groups for channel AC
AC
19
SYNC2_A2_OOS
Dual channel synchronization of channels AC and AD not successful if 1
AD
29
CV_AD_OR
Code violation in one or more of the received 10-bit groups for channel AD
AD
19
SYNC8_OOS
Eight channel synchronization not successful if 1
BA
29
CV_BA_OR
Code violation in one or more of the received 10-bit groups for channel BA
BA
19
SYNC2_B1_OOS
Dual channel synchronization of channels BA and BB not successful if 1
BB
29
CV_BB_OR
Code violation in one or more of the received 10-bit groups for channel BB
BB
19
SYNC4_B_OOS
Quad channel synchronization of SERDES quad A not successful if 1
BC
29
CV_BC_OR
Code violation in one or more of the received 10-bit groups for channel BD
BC
19
SYNC2_B2_OOS
Dual channel synchronization of channels BC and BD not successful if 1
BD
29
CV_BD_OR
Code violation in one or more of the received 10-bit groups for channel BD
BD
19
SYNC8_OOS
Eight channel synchronization not successful if 1
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