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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 51/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
55
30820 - Ax
30920 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
FMPU_RESYNC1
_xx
00
Resync a Single Channel. When FMPU_RESYNC1_xx transitions from
0 to 1, the corresponding channel is resynchronized (the write and read
pointers are reset).
FMPU_STR_EN_xx=0 on device reset.
[4]
xA & xB
[5] xC & xD
FMPU_RESYNC2
_A1
00
Resync a Pair of Channels. When FMPU_RESYNC2_[A:B][1:2] transi-
tions from a 0 to a 1, the corresponding channel pair is resynchronized.
FFMPU_RESYNC2_[A:B][1:2=0 on device reset.
[6]
FMPU_RESYNC4
[A:B]
00
Resync a Four-Channel Group. When FMPU_RESYNC4[A:B] transitions
from a 0 to a 1, the corresponding four-channel group is resynchronized.
FMPU_RESYNC4[A:B]=0 on device reset.
[7]
XAUI_MODE[A:B]
00
Controls use of XAUI link state machine in place of Fibre-Channel state
machine. When XAUI_MODE[A:B]=1, all four channels in the SERDES
quad enable their XAUI link state machines. (LINKSM_xx bits are
ignored).
XAUI_MODE[A:B]=0 on device reset.
30821 - A
30921 - B
[0]
NOCHALGN [A:B]
Bypass channel alignment. NOCHALGN [A:B] =1 causes bypassing of
multi-channel alignment FIFOs for the corresponding SERDES quad.
NOCHALGN [A:B] =0 on device reset.
[1:7]
Reserved for future use
30822
[0:7]
Reserved for future use
30832
[0:7]
Reserved for future use
30833
[0:7]
Reserved for future use
30933
[0:3]
Reserved for future use
[4:5]
SCHAR_CHAN[0:
1]
00
Select channel to test
00 = Channel BA
10 = Channel BB
01 =Channel BC
11 = Channel BD
[6]
SCHAR_TXSEL
1=Select TX option
0=Select RX option
[7]
SCHAR_ENA
1=Enable Characterization of SERDES B
Status Registers (Read Only), xx=[AA, ...,BD]
30804 - Ax
30904 - Bx
[0:1]
xA
[2:3]
xB
[4:5]
xC
[6:7]
xD
XAUISTAT_xx[0:1]
00
XAUI Status Register. Status of XAUI link state machine for Channel xx
00—No synchronization.
10—Synchronization done.
01,11—Not used.
XAUISTAT_xx[0:1] = 00 on device reset.
30805 - Ax
30905 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
DEMUXWAS_xx
00
Status of Word Alignment. When DEMUX_WAS_xx=1, word alignment is
achieved for Channel xx.
DEMUX_WAS_xx=0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
CH248_SYNC_xx
Status of Channel Alignment. When CH248_SYNC_xx=1, multi-channel
alignment is achieved for Channel xx.
CH248_SYNC_xx=0 on device reset.
30806
30906
[0:7]
Reserved for future use
Table 20. Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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