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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 54/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
58
Common Control Registers (Read/Write)
30A000
[0:1]
TCKSELA
00
Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES
quad A
00 = Channel AA
10 = Channel AB
01 = Channel AC
11 = Channel AD
[2:3
RCKSELA
Receive Clock Select. Controls source of 78 MHz RCK78 for SEDRES
quad A
00 = Channel AA
10 = Channel AB
01 = Channel AC
11 = Channel AD
[4:5]
TCKSELB
Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES
quad B
00 = Channel BA
10 = Channel BB
01 = Channel BC
11 = Channel BD
[6:7}
RCKSELB
Receive Clock Select. Controls source of 78 MHz RCK78 for SERDES
quad B
00 = Channel BA
10 = Channel BB
01 = Channel BC
11 = Channel BD
30A01
[0:4]
Reserved for future use
[5:7]
RX_FIFO_MIN
00
Threshold for low address in RX_FIFO’s
RX_FIFO_MIN Bits x, y, z.*
30A02
[0:1]
RX_FIFO_MIN
00
Threshold for low address in RX_FIFO’s
RX_FIFO_MIN Bits u, w.*
[2]
FMPU_RESYNC8
Resynchronize and eight-channel group. When FPMPU_RESYNC8
transitions from A0 to A1, the entire eight-channel group is resynchro-
nized.
FMPU_RESYNC0 = 0 on device reset
[3:7]
Reserved for future use
Common Status Registers xx=[AA, ...,BD]
30A04
[0]
SYNC8_OVFL
00
Read-Only Multi-Channel Overow Status. When SYNC8_OVFL=1, 8-
channel synchronization FIFO overow has occurred.
SYNC8_OVFL=0 on device reset.
[1]
SYNC8_OOS
Read-Only Multi-Channel Out-Of-Sync Status. When SYNC8_OOS=1,
8-channel synchronization has failed.
SYNC8_OOS=0 on device reset.
[2:7]
Reserved for future use
30A05
Reserved for future use
* RX_FIFO_MIN {0:4} = Bits [w, v, z, y, x], Useful Values: 0:17(decimal)
Table 20. Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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