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| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 44/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
49
Table 18. Embedded Memory Slice Core/FPGA Interface Signal Description
Memory Map
Denition of Register Types
The registers in ORT82G5 are 8-bit memory locations, which in general can be classied into the following types:
Status Register and Control Register.
Status Register
Read-only register to convey the status information of various operations within the FPSC core. An example is the
state of the XAUI link-state-machine.
Control Register
Read-write register to set up the control inputs that dene the operation of the FPSC core.
The SERDES block within the ORT82G5 core has a set of status and control registers for its operation. There is
another group of status and control registers which are implemented outside the SERDES, which are related to the
SERDES and other functional blocks in the FPSC core. Reserved addresses for register blocks are shown in
Table 19. The registers will be described in detail here.
Each SERDES has four independent channels, which are named A, B, C, or D. Using this nomenclature, the SER-
DES A channels are named as AA, AB, AC, and AD, while SERDES B channels will be BA, BB, BC, and BD.
Table 19. Structural Register Elements
A full memory map is included in Table 20.
Table 20 details the memory map for the FPSC portion of the ORT82G5 device.
Addresses for the control registers for the FPGA portion of the device are detailed in the ORCA Series 4 data
sheet. This table shows the databus oriented for the PPC interface. DB0 is the MSB, while DB7 is the LSB. If the
FPGA/Embedded Core
Interface Signal Name]
Input (I) to or
Output (O)
from Core
Signal Description
Memory Slice Interface Signals
D_[A:B][35:0]
I
Data in—memory slice [A:B]
CKW_[A:B]
I
Write clock—memory slice [A:B].
CSWA_[A:B]
I
Write chip select for SRAM A—memory slice [A:B].
CSWB_[A:B]
I
Write chip select for SRAM B—memory slice [A:B].
AW_[A:B][10:0]
I
Write address—memory slice [A:B].
BYTEWN_[A:B][3:0]
I
Write control pins for byte-at-a-time write-memory slice [A:B].
Q_[A:B][35:0]
O
Data out—memory slice [A:B].
CKR_[A:B]
I
Read clock—memory slice [A:B].
CSR_[A:B]
I
Read chip select—memory slice [A:B]. CSR_[A:B]= 0 selects SRAM A.
CSR_[A:B]= 1 selects SRAM B.
AR_[A:B][10:0]
I
Read address—memory slice [A:B].
Address (0x)
Description
300xx
SERDES A, internal registers.
301xx
SERDES B, internal registers.
308xx
Channel A [A:D] registers (external to SERDES blocks).
309xx
Channel B [A:D] registers (external to SERDES blocks).
30A0x
Global registers (external to SERDES blocks).
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