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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 41/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
46
4.
Enable PRBS by setting PRBS_xx register bits (30004,30014, 30024, 30034, 30104, 30114, 30124, 30134).
Alternately, the GPRBS_[A,B] bits can be used to enable PRBS test for all 4 SERDES channels within a bank
(registers 30005, 30105).
5.
Assert GSWRST_[A,B] bits (registers 30005, 30105) by writing two ones to reset the transmit and receive
logic. Then clear the reset bits by writing two 0s.
6.
Monitor the PRBSCHK_xx and PRBSTOUT_xx (30000,30010, 30020, 30030, 30100, 30120, 30130, 30140)
alarm bits.
SERDES Characterization Test Mode
The SERDES characterization mode is a test mode that allows for direct control and observation of the transmit
and receive SERDES interfaces at chip ports. With these modes the SERDES logic and I/O can be tested one
channel at a time in either the receive or transmit modes. The SERDES characterization mode is available for only
one quad (quad B) of the ORT82G5.
The characterization test mode is congured by setting bits in the control registers via the system bus. There are 4
bits that set up the test mode. The transmit characterization test mode is entered when SCHAR_ENA=1 and
SCHAR_TXSEL=1. Entering this mode will cause chip port inputs to directly control the SERDES low-speed trans-
mit ports of one of the channels as shown in Table 15.
Table 15. SERDES Transmit Characterization Mode
The x in the table will be a single channel in SERDES quad B, selected by the SCHAR_CHAN control bits. The
decoding of SCHAR_CHAN is shown in Table 16.
Table 16. Decoding of SCHAR_CHAN
The receive characterization test mode is entered when SCHAR_ENA=1 and SCHAR_TXSEL=0, In this mode,
one of the channels of SERDES outputs is observed at chip ports as shown in Table 17. The channel that is
observed is also based on the decoding of SCHAR_CHAN as shown in Table 17.
Table 17. SERDES Receive Characterization Mode
Chip Port
SERDES Input
PSCHAR_CKIO0
TBCBx
PSCHAR_LDIO[9:0]
LDINBx[9:0]
SCHAR_CHAN0
SCHAR_CHAN1
Channel
0
BA
1
0
BB
0
1
BC
1
BD
SERDES Output
Chip Port
BYTSYNCBx
PSCHAR_BYTSYNC
WDSYNCBx
PSCHAR_WDSYNC
CVOBx
PSCHAR_CV
LDOUTBx[9:0]
PSCHAR_LDIO[9:0]
RBC0Bx
PSCHAR_CKIO0
RBC1Bx
PSCHAR_CKIO1
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