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| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 27/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
33
Table 9. Transceiver Embedded Core/FPGA Interface Signal Description
ORT82G5 Reference Clocks and Internal Clock Distribution
Reference Clock Requirements
There are two pairs of reference clock inputs on the ORT82G5. The differential reference clock is distributed to all
four channels in a quad. Each channel has a differential buffer to isolate the clock from the other channels. The
input clock is preferably a differential signal; however, the device can operate with a single-ended input. The input
reference clock directly impacts the transmit data eye, so the clock should have low jitter. In particular, jitter compo-
nents in the DC to 5 MHz range should be minimized. The required electrical characteristics for the reference clock
are given in Table 24.
Note: In sections of this data sheet, the differential clocks are simply referred to as the reference clock as
REFCLK_[A:B]. REFCLK_[A:B] is equivalent to REFINP_[A:B] and REFINN_[A:B].
Synthesized and Recovered Clocks
The SERDES Embedded Core block contains its own dedicated PLLs for transmit and receive clock generation.
The user provides a reference clock of the appropriate frequency, as described in the previous section. The trans-
mitter PLL uses the REFCLK_[A,B] inputs to synthesize the internal high-speed serial bit clocks. The receiver PLLs
extract the clock from the serial input data and retime the data with the recovered clock.
The receive PLL for each channel has two modes of operation - lock to reference and lock to data with retiming.
When no data or invalid data is present on the HDINP_xx and HDINN_xx pins, the receive VCO will not lock to data
and its frequency can drift outside of the nominal ±100 ppm range. Under this condition, the receive PLL will lock to
REFCLK_[A,B] for a xed time interval and then will attempt to lock to receive data. The process of attempting to
lock to data, then locking to clock will repeat until valid input data exists. There is also a control register bit per
channel to force the receive PLL to always lock to the reference clock.
The high-speed transmit and receive serial data links can run at 1.0 to 3.7 Gbits/s, depending on the frequency of
the reference clock and the state of the control bits from the internal transmit control register. The interface to the
serializer/deserializer block runs at 1/10th the bit rate of the data lane. Additionally, the MUX/DEMUX logic converts
FPGA/Embedded Core Inter-
face Signal Name
(xx = [AA, ... ,BD])
Input (I) to or
Output (O)
from Core
Signal Description
Transmit Path Signals
TWDxx[31:0]
I
Transmit data—channel xx.
TCOMMAxx[3:0]
I
Transmit comma character—channel xx.
TBIT9xx[3:0]
I
Transmit force negative disparity—channel xx
TSYS_CLK_xx
I
Transmit low-speed clock to the FPGA—channel xx
TCK78[A:B]
O
Transmit low-speed clock to the FPGA—SERDES Quad [A:B].
Receive Path Signals
MRWDxx[39:0]
O
Receive data—Channel xx (see ).
RWCKxx
O
Low-speed receive clock—Channel xx.
RCK78[A:B]
O
Receive low-speed clock to FPGA—SERDES Quad [A:B].
RSYS_CLK_A1
I
Low-speed receive FIFO clock for channels AA, AB
RSYS_CLK_A2
I
Low-speed receive FIFO clock for channels AC, AD
RSYS_CLK_B1
I
Low-speed receive FIFO clock for channels BA, BB
RSYS_CLK_B2
I
Low-speed receive FIFO clock for channels BC, BD
CV_SELxx
Enable detection of code violations in the incoming data
SYS_RST_N
I
Synchronous reset of the channel alignment blocks.
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