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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 35/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
40
Figure 22. Clocking for Eight Channel Alignment
Reset Operation
The SERDES block can be reset in one of three different ways as follows: on power up, using the hardware reset,
or via the microprocessor interface. The power up reset process begins when the power supply voltage ramps up to
approximately 80% of the nominal value of 1.5 V. Following this event, the device will be ready for normal operation
after 3 ms.
A hardware reset is initiated by making the PASB_RESETN low for at least two microprocessor clock cycles. The
device will be ready for operation 3 ms after the low to high transition of the PASB_RESETN. This reset function
affects all SERDES channels and resets all microprocessor and internal registers and counters.
Using the software reset option, each channel can be individually reset by setting SWRST (bit 2) to a logic 1 in the
channel conguration register. The device will be ready 3 ms after the SWRST bit is deasserted. Similarly, all four
channels per quad SERDES can be reset by setting the global reset bit GSWRST. The device will be ready for nor-
mal operation 3 ms after the GSWRST bit is deasserted. Note that the software reset option resets only SERDES
internal registers and counters. The microprocessor registers are not affected. It should also be noted that the
embedded block cannot be accessed until after FPGA conguration is complete.
Start Up Sequence
The following sequence is required by the ORT82G5 device. For information required for simulation that may be dif-
ferent than this sequence, see the ORT82G5 design kit.
FPGA
Logic
Common Logic, Quad A
Channel AA
Channel AB
Channel AD
Channel AC
Common Logic, Quad B
Channel BA
Channel BB
Channel BD
Channel BC
RCK78A
TCK78A
RSYS_CLK_A1
TSYS_CLK_AA
RWCKAA
RWCKAB
TSYS_CLK_AB
RWCKAC
TSYS_CLK_AC
RSYS_CLK_A2
TSYS_CLK_AD
RWCKAD
RCK78B
TCK78B
RSYS_CLK_B1
TSYS_CLK_BA
RWCKBA
RWCKBB
TSYS_CLK_BB
RSYS_CLK_B2
RWCKBD
RWCKBC
TSYS_CLK_BC
TSYS_CLK_BD
TCK78A
2
REFCLK[P:N]_A
2
REFCLK[P:N]_B
156.25 MHz
All Clocks at
78.125 MHZ
Eight Bidirectional
Channels of 3.125
Gbits/s Serial Data
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