- 您现在的位置：买卖IC网 > PDF目录180051 > M-ORT82G52BM680-DB (LATTICE SEMICONDUCTOR CORP) FPGA, 1296 CLBS, 333000 GATES, PBGA680 PDF资料下载
参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 8/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
16
Figure 5. ORT82G5 Transmit Path Timing - Single SERDES Channel
Each quad also sends a clock to the FPGA logic. This clock, TCK78[A,B], is sourced from one of the four MUX
blocks and has the same frequency as TSYS_CLK_xx, but arbitrary phase. Within each MUX block, the low fre-
quency clock output is obtained by dividing by 4 the SERDES STBC311x clock which is used internally to synchro-
nize the transmit data words. TCKSEL control bits select the channel to source TCK78[A:B].
The internal signals STBDxx[9:0] (where xx is represents AA—BD) from the MUX block carry unencoded character
data and control bits. The 10th bit (STBDxx[9]) of each data lane into the SERDES is used to force negative dispar-
ity encoding.
8b/10b Encoder and 1:10 Multiplexer
The 8b/10b encoder encodes the incoming 8-bit data into a 10-bit format as described previously. The input signals
to the block, STBDxx[7:0] are used for the 8 bit unencoded data. STBDxx[8] is used as the K_control input to indi-
cate whether the 8 data bits need to be encoded as special characters (K_control = 1) or as data characters
(K_control = 0). When STBDxx[9:0] = 1, negative disparity encoding is forced. When the encoder is bypassed STB-
Dxx[9:0] serve as the data bits for the 10-bit unencoded data.
Within the denition of the 8b/10b transmission code, the bit positions of the 10-bit encoded transmission charac-
ters are labeled as a, b, c, d, e, i, f, g, h, and j in that order. Bit a corresponds to STBDxx[0], bit b to STBDxx[1], bit
c to STBDxx[2], bit d to STBDxx[3], bit e to STBDxx[4], bit i to STBDxx[5], bit f to STBDxx[6], bit g to STBDxx[7], bit
h to STBDxx[8], and bit j to STBDxx[9].
The 10-bit wide parallel data is converted to serial data by the 10:1 Multiplexer. The serial data are then sent to the
CML output buffer and are transmitted serially with STBDxx[0] transmitted rst and STBDxx[9] transmitted last.
CML Output Buffer
The transmitter’s CML output buffer is terminated on-chip in 86 ohms to optimize the data eye as well as to reduce
the number of discrete components required. The differential output swing reaches a maximum of 1.2 VPP in the
normal amplitude mode. A half amplitude mode can be selected via conguration register bit HAMP_xx. Half ampli-
tude mode can be used to reduce power dissipation when the transmission medium has minimal attenuation or for
testing of the integrity (loss) of the physical medium.
A programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maxi-
mize the data eye opening at the far-end receiver. Preemphasis is particularly useful when the data are transmitted
over backplanes or low-quality coax cables which have a frequency-dependent amplitude loss. For example, for
FR4 material at 2.5 GHz, the attenuation compared to the 1.0 GHz value is about 3 dB. The attenuation is a result
of skin effect loss of the PCB conductor and the dielectric loss of the PCB substrate. This attenuation causes inter-
symbol interface which results in the closing of the data eye opening at the receiver.
.....
pq
r
s
t
x
y
z
STBDxx[9:0]
.....
STBC311xx
.....
HDOUT_xx
p
4
p
5
p
6
p
7
p
8
p
9
p
0
p
1
p
2
p
3
LATENCY =
5 STBC311x CLOCKS
相关PDF资料 |
PDF描述 |
|---|---|
| M.PI-1R1D12 | 1 ELEMENT, 1.1 uH, GENERAL PURPOSE INDUCTOR, SMD |
| M01-014-1452PA | 14 CONTACT(S), MALE, RIGHT ANGLE TELECOM AND DATACOM CONNECTOR, SOLDER |
| M01-016-1443PA | 16 CONTACT(S), MALE, RIGHT ANGLE TELECOM AND DATACOM CONNECTOR, SOLDER |
| M0302CS-9N2XJSU | 1 ELEMENT, 0.0092 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD |
| M0302CS-7N4XJSW | 1 ELEMENT, 0.0074 uH, CERAMIC-CORE, GENERAL PURPOSE INDUCTOR, SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MORTAR-44LB | 制造商:3M Electronic Products Division 功能描述:3M(TM) FIRE BARRIER MORTAR, 44 98040056073 制造商:3M Electronic Products Division 功能描述:Fire Barrier 44 lb Bag |
| MO-RX3930 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
| MO-RX3930-FS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
| MO-RX3930-FS315M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
| MO-RX3930-FS434M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FSK RECEIVER MODULE |
发布紧急采购，3分钟左右您将得到回复。