参数资料
型号: NT5CB256M4AN-BF
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA78
封装: 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78
文件页数: 10/106页
文件大小: 2599K
代理商: NT5CB256M4AN-BF
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
11
REV 1.2
01 / 2009
DDR3 Reset and Initialization Sequence at Power-on Ramping
CK
tCKSRX
RESET
CKE
tIS
ODT
Command
BA0-BA2
T=200us
T=500us
tXPR
tMRD
tMOD
tZQinit.
Do Not
Care
Time break
10ns
MRS
ZQCL
MR2
MR3
MR1
MR0
VDD,
VDDQ
* From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads.
Te
Tk
NOP*
Valid
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
Td
Tc
Ta
Tb
Tf
Tg
Th
Ti
Tj
tDLLK
Valid
DDR3 Reset Procedure at Power Stable Condition
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be maintained
for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns).
2. Follow Power-up Initialization Sequence step 2 to 11.
3. The Reset sequence is now completed. DDR3 SDRAM is ready for normal operation.
CK
tCKSRX
RESET
CKE
tIS
ODT
Command
BA0-BA2
T=100ns
T=500us
tXPR
tMRD
tMOD
tZQinit.
Do Not
Care
Time break
10ns
MRS
ZQCL
MR2
MR3
MR1
MR0
VDD,
VDDQ
* From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads.
Te
Tk
NOP*
Valid
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
Td
Tc
Ta
Tb
Tf
Tg
Th
Ti
Tj
tDLLK
Valid
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