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| 型号： | NT5CB256M4AN-BF |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA78 |
| 封装： | 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78 |
| 文件页数： | 13/106页 |
| 文件大小： | 2599K |
| 代理商： | NT5CB256M4AN-BF |
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1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
14
REV 1.2
01 / 2009
Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as shown in
the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting
column address. The burst length is defined by bits A0-A1. Burst length options include fix BC4, fixed BL8, and on the fly which allow
BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/
.
Burst Type and Burst Order
Burst Length Read/ Write
Starting Column Address
(A2,A1,A0)
Burst type = Sequential
(decimal)
A3 = 0
Burst type = Interleaved
(decimal)
A3 = 1
Note
000
0,1,2,3,T,T,T,T
001
1,2,3,0,T,T,T,T
1,0,3,2,T,T,T,T
010
2,3,0,1,T,T,T,T
011
3,0,1,2,T,T,T,T
3,2,1,0,T,T,T,T
100
4,5,6,7,T,T,T,T
101
5,6,7,4,T,T,T,T
5,4,7,6,T,T,T,T
110
6,7,4,5,T,T,T,T
111
7,4,5,6,T,T,T,T
7,6,5,4,T,T,T,T
0,V,V
0,1,2,3,x,x,x,x
1,V,V
4,5,6,7,x,x,x,x
0
0,1,2,3,4,5,6,7
1
1,2,3,0,5,6,7,4
1,0,3,2,5,4,7,6
10
2,3,0,1,6,7,4,5
11
3,0,1,2,7,4,5,6
3,2,1,0,7,6,5,4
100
4,5,6,7,0,1,2,3
101
5,6,7,4,1,2,3,0
5,4,7,6,1,0,3,2
110
6,7,4,5,2,3,0,1
111
7,4,5,6,3,0,1,2
7,6,5,4,3,2,1,0
Write
V,V,V
0,1,2,3,4,5,6,7
2,4
Note:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than the
BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length
being selected on-th-fly via A12/
, the internal write operation starts at the same point in time like a burst of 8 write
operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
2. 0~7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Do not Care.
Write
Read
4
Chop
1,2,3
1,2,4,5
Read
2
8
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5CB256M8FN-DI | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5CB256M8GN-CG | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16DP-CF | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16FP-DH | 制造商:Nanya Technology Corporation 功能描述:MEMORY |
| NT5CB64M16FP-DII | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
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