1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
34
REV 1.2
01 / 2009
READ Operation
Read Burst Operation
During a READ or WRITE command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (AUTO
PRECHARGE can be enabled or disabled).
A12=0, BC4 (BC4 = burst chop, tCCD=4)
A12=1, BL8
A12 will be used only for burst length control, not a column address.
Read Burst Operation RL=5 (AL=0, CL=5, BL=8)
READ Burst Operation RL = 9 (AL=4, CL=5, BL=8)
READ Timing Definitions
Read timing is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK.
tDQSCK is the actual position of a rising strobe edge relative to CK, CK.
tQSH describes the DQS,
differential output high time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalide transition of the associated DQ pins.
Falling data strobe edge parameters:
tQSL describes the DQS,
differential output low time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
CK
T0
T1
T3
T5
T6
T7
T9
T145
CL=5
DQS, DQS
T2
T4
T8
T10
READ
NOP
CMD
NOP
Bank
Col n
Address
Dout
n
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
Dout
n +6
Dout
n +7
DQ
RL = AL + CL
tRPRE
tRPST
CK
T0
T1
T3
T5
T6
T7
T9
T145
CL=5
DQS, DQS
T2
T4
T8
T10
READ
NOP
CMD
NOP
Bank
Col n
Address
Dout
n
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
DQ
RL = AL + CL
tRPRE
AL = 4