参数资料
型号: NT5CB256M4AN-BF
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA78
封装: 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78
文件页数: 11/106页
文件大小: 2599K
代理商: NT5CB256M4AN-BF
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
12
REV 1.2
01 / 2009
Register Definition
Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the DDR3
SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As the default values of
the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e. written, after
power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by re-executing the MRS
command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the
MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS
command and DLL Reset do not affect array contents, which means these commands can be executed any time after power-up
without affecting the array contents
The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum
time required between two MRS commands shown as below.
CK
CKE
Do not
Care
Time break
MRS
NOP
CMD
VAL
ADDR
tMRD
MRS
The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL reset, and is the
minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the following figure.
CK
CKE
MRS
NOP
CMD
ADDR
tMOD
Non
MRS
VAL
Old Setting
Updating Setting
New Setting
VAL
The mode register contents can be changed using the same command and timing requirements during normal operation as long as
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