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| 型号： | NT5CB256M4AN-BF |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA78 |
| 封装： | 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78 |
| 文件页数： | 28/106页 |
| 文件大小： | 2599K |
| 代理商： | NT5CB256M4AN-BF |
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1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
28
REV 1.2
01 / 2009
Change Frequency during Precharge Power-down
Write Leveling
For better signal integrity, DDR3 memory adopted fly by topology for the commands, addresses, control signals, and clocks. The fly by
topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clock and
strobe at every DRAM on DIMM. It makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the
controller should support “write leveling” in DDR3 SDRAM to compensate the skew.
The memory controller can use the “write leveling” feature and feedback from the DDR3 SDRAM to adjust the DQS - to CK -
relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS -
to align the rising edge
of DQS -
with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK - , sampled with the rising edge of
DQS -
, through the DQ bus. The controller repeatedly delays DQS - until a transition from 0 to 1 is detected. The DQS -
delay established though this exercise would ensure tDQSS specification. Besides tDQSS, tDSS, and tDSH specification also needs
to be fulfilled. One way to achieve this is to combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the
DQS-
signals. Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better
than the absolute limits provided in “AC Timing Parameters” section in order to satisfy tDSS and tDSH specification. A conceptual
timing of this scheme is show as below figure.
0 or 1
0
Diff _ CK
Diff _DQS
Source
Diff _ CK
Diff _ DQS
Destination
DQ
Push DQS to capture
0 -1 transition
0 or 1
1
CK
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Td1
Te0
CKE
Command
DQS,
DQS
tCH
tCL
tCK
Te1
tIH
tIS
tIH
tIS
tCKSRE
tCKE
tCKSRX
tCHb
tCLb
tCKb
NOP
MRS
NOP
Valid
DLL
Reset
Valid
tIH
tIS
Address
ODT
DQ
DM
High-Z
tAOFPD/tAOF
tCPDED
tXP
tDLLK
Previous Clock Frequency
New Clock Frequency
Frequency
Change
Enter Precharge
Power-Down mode
Exit Precharge
Power-Down mode
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PDF描述 |
|---|---|
| NT5DS64M8BF-6KI | DDR DRAM, PBGA60 |
| NT5SE8M16DS-6K | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| NT5SV8M8DT-7 | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NTC1111-20MHZ | Analog IC |
| NTC1111-SERIES | Analog IC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5CB256M8FN-DI | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5CB256M8GN-CG | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16DP-CF | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16FP-DH | 制造商:Nanya Technology Corporation 功能描述:MEMORY |
| NT5CB64M16FP-DII | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
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