- 您现在的位置：买卖IC网 > PDF目录189259 > NT5CB256M4AN-BF (NANYA TECHNOLOGY CORP) DDR DRAM, PBGA78 PDF资料下载
参数资料
| 型号： | NT5CB256M4AN-BF |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA78 |
| 封装： | 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78 |
| 文件页数： | 29/106页 |
| 文件大小： | 2599K |
| 代理商： | NT5CB256M4AN-BF |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
29
REV 1.2
01 / 2009
DQS/
driven by the controller during leveling mode must be determined by the DRAM based on ranks populated. Similarly, the DQ
bus driven by the DRAM must also be terminated at the controller.
One or more data bits should carry the leveling feedback to the controller across the DRAM configurations x4, x8, and x16. On a x16
device, both byte lanes should be leveled independently. Therefore, a separate feedback mechanism should be able for each byt e
lane. The upper data bits should provide the feedback of the upper diff_DQS (diff_UDQS) to clock relationship whereas the lower data
bits would indicate the lower diff_DQS (diff_LDQS) to clock relationship.
DRAM setting for write leveling and DRAM termination unction in that mode
DRAM enters into Write leveling mode
if A7 in MR1 set “High” and after finishing leveling, DRAM exits from write leveling mode if A7 in
MR1 set “Low”. Note that in write leveling mode, only DQS/ terminations are activated and deactivated via ODT pin not like normal
operation.
MR setting involved in the leveling procedure
Function
MR1
Enable
Disable
Write leveling enable
A7
1
0
Output buffer mode (Qoff)
A12
0
1
DRAM termination function in the leveling mode
ODT pin at DRAM
DQS/DQS termination
DQs termination
De-asserted
off
Asserted
on
off
Note: In write leveling mode with its output buffer disabled (MR1[bit7]=1 with MR1[bit12]=1) all RTT_Nom settings are allowed; in Write
Leveling Mode with its output buffer enabled (MR1[bit7]=1 with MR1[bit12]=0) only RTT_Nom settings of RZQ/2, RZQ/4, and RZQ/6
are allowed.
Procedure Description
Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. With entering write leveling mode, the DQ pins are
in undefined driving mode. During write leveling mode, only NOP or Deselect commands are allowed. As well as an MRS command to
exit write leveling mode. Since the controller levels one rank at a time, the output of other rank must be disabled by setting MR1 bit A12
to 1. Controller may assert ODT after tMOD, time at which DRAM is ready to accept the ODT signal.
Controller may drive DQS low and
high after a delay of tWLDQSEN, at which time DRAM has applied on-die termination on these
signals. After tDQSL and tWLMRD controller provides a single DQS,
edge which is used by the DRAM to sample CK – driven
from controller. tWLMRD(max) timing is controller dependent.
DRAM samples CK -
status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after tWLO timing.
There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read strobes (DQS/DQS) needed for
these DQs. Controller samples incoming DQ and decides to increment or decrement DQS
– delay setting and launches the next
DQS/
pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the controller locks DQS –
delay setting and write leveling is achieved for the device. The following figure describes the timing diagram and parameters for the
overall Write leveling procedure.
相关PDF资料 |
PDF描述 |
|---|---|
| NT5DS64M8BF-6KI | DDR DRAM, PBGA60 |
| NT5SE8M16DS-6K | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| NT5SV8M8DT-7 | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NTC1111-20MHZ | Analog IC |
| NTC1111-SERIES | Analog IC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5CB256M8FN-DI | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5CB256M8GN-CG | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16DP-CF | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16FP-DH | 制造商:Nanya Technology Corporation 功能描述:MEMORY |
| NT5CB64M16FP-DII | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
发布紧急采购，3分钟左右您将得到回复。