参数资料
型号: NT5CB256M4AN-BF
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA78
封装: 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78
文件页数: 21/106页
文件大小: 2599K
代理商: NT5CB256M4AN-BF
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
21
REV 1.2
01 / 2009
Mode Register MR3
The Mode Register MR3 controls Multi purpose registers. The Mode Register 3 is written by asserting low on
, , , high
on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table below.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
BA2
Address Filed
MRS mode
BA0
BA1
MR0
0
1
0
MRS mode
0
1
Note: BA2, A3-A13 are reserved for future use and must be
set to 0 when programming the MR.
MR1
MR2
MR3
MPR
A2
Normal Operation
0
Dataflow from MPR
1
MPR
MPR Loc.
A0
A1
0
RFU
0
MPR Location
Predefined pattern
1
0
1
RFU
Thermal Sensor Readout
Multi-Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To enable the
MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the MRS command, all
banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands
will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent
MRS command is issued with the MPR disabled (MR3 bit A2=0). Power down mode, Self-Refresh, and any other non-RD/RDA
command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode.
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