参数资料
型号: NT5CB256M4AN-BF
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA78
封装: 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78
文件页数: 20/106页
文件大小: 2599K
代理商: NT5CB256M4AN-BF
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
20
REV 1.2
01 / 2009
Partial Array Self-Refresh (PASR)
If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range shown in MR2
will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met and no Self-Refresh command is
issued.
CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock cycles, between the
internal Write command and the availability of the first bit of input data. DDR3 DRAM does not support any half clock latencies. The
overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL); WL=AL+CWL.
Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT)
DDR3 SDRAM must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation in the
Extended Temperature Range must use the ASR function or program the SRT bit appropriately.
Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal integrity on the
data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. MR2
Register locations A9 and A10 configure the Dynamic ODT settings.
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