参数资料
型号: NT5CB256M4AN-BF
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA78
封装: 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78
文件页数: 37/106页
文件大小: 2599K
代理商: NT5CB256M4AN-BF
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
36
REV 1.2
01 / 2009
Read Timing; Data Strobe to Data Relationship
The Data Strobe to Data relationship is shown in the following figure and is applied when the DLL and enabled and locked.
Rising data strobe edge parameters:
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Data Strobe to Data Relationship
Dout
n +6
Dout
n +7
tRPST
CK
T0
T1
T3
T5
T6
T7
T9
DQS, DQS
T2
T4
T8
READ
NOP
CMD
NOP
Bank
Col n
Address
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
DQ (Last data valid)
RL = AL + CL
tRPRE
Dout
n +6
Dout
n +7
Dout
n
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
tLZ(DQ)min
Valid data
tHZ(DQ)min
tDQSQmax
Valid data
tQH
Dout
n
tDQSQmin
DQ (First data no
longer valid)
All DQ collectively
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