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| 型号： | NT5CB256M4AN-BF |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA78 |
| 封装： | 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78 |
| 文件页数： | 4/106页 |
| 文件大小： | 2599K |
| 代理商： | NT5CB256M4AN-BF |
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1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
101
REV 1.2
01 / 2009
Data Setup, Hold, and Slew Rate Derating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDH(base) and
tDH(base) value to the delta tDS and delta tDH derating value respectively.
Example: tDS (total setup time) = tDS(base) + delta tDS
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the first crossing
of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vref(dc) and
the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded Vref(dc) to ac
region, use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded
Vref(dc) to ac region, the slew rate of the tangent line to the actual signal from the ac level to dc level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the fi
rst crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line between shaded dc
level to Vref(dc) region, use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere
between shaded dc to Vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to Vref(dc) level is used for
derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time
of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in the following tables, the derating values may be obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Data Setup and Hold Base-Values
Unit [ps]
DDR3-800
(-AC/-AD)
DDR3-1066
(-BE/-BF)
DDR3-1333
(-CF/-CG)
DDR3-1600
(-DG/-DH)
reference
tDS(base)
75
25
-10
VIH/L(ac)
tDH(base)
150
100
65
VIH/L(dc)
Note: ac/dc referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate
相关PDF资料 |
PDF描述 |
|---|---|
| NT5DS64M8BF-6KI | DDR DRAM, PBGA60 |
| NT5SE8M16DS-6K | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| NT5SV8M8DT-7 | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NTC1111-20MHZ | Analog IC |
| NTC1111-SERIES | Analog IC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5CB256M8FN-DI | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5CB256M8GN-CG | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16DP-CF | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16FP-DH | 制造商:Nanya Technology Corporation 功能描述:MEMORY |
| NT5CB64M16FP-DII | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
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