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参数资料
| 型号： | NT5CB256M4AN-BF |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA78 |
| 封装： | 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78 |
| 文件页数： | 25/106页 |
| 文件大小： | 2599K |
| 代理商： | NT5CB256M4AN-BF |
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1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
25
REV 1.2
01 / 2009
DLL on/off switching procedure
DDR3 DLL-
off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit set back to
“0”.
DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires te frequency to be changed during Self-Refresh outlined in the following procedure:
1.
Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT, must be in high
impedance state before MRS to MR1 to disable the DLL).
2.
Set MR1 Bit A0 to “1” to disable the DLL.
3.
Wait tMOD.
4.
Enter Self Refresh Mode; wait until (tCKSRE) satisfied.
5.
Change frequency, in guidance with “Input Clock Frequency Change” section.
6.
Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
7.
Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from any MRS
command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode was
entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS command are satisfied. If
both ODT features were disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered
LOW or HIGH.
8.
Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be necessary. A
ZQCL command may also be issued after tXS).
9.
Wait for tMOD, and then DRAM is ready for next command.
DLL Switch Sequence from DLL-on to DLL-off
CK
T0
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te 0
Te1
MRS 2)
1)
CMD
CKE
ODT
tMOD
Tf0
tCKSRE
4)
tCKSRX 5)
tXS
tMOD
NOP
SRE 3)
NOP
SRX 6)
NOP
MRS 7)
NOP
Valid 8)
tCKESR
Valid 8)
Time
break
Do not
Care
Note:
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
1) Starting with Idle State, RTT in Hi-Z State.
2) Disable DLL by setting MR1 Bit A0 to 1.
3) Enter SR.
4) Change Frequency.
5) Clock must be stable at least tCKSRX.
6) Exit SR.
7) Update Mode registers with DLL off parameters setting.
8) Any valid command.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5CB256M8FN-DI | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5CB256M8GN-CG | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16DP-CF | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16FP-DH | 制造商:Nanya Technology Corporation 功能描述:MEMORY |
| NT5CB64M16FP-DII | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
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