参数资料
型号: NT5CB256M4AN-BF
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA78
封装: 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78
文件页数: 8/106页
文件大小: 2599K
代理商: NT5CB256M4AN-BF
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
105
REV 1.2
01 / 2009
Revision Log
Rev
Date
Modification
0.1
04/2008
Preliminary Release
0.2
05/2008
Updated Simplified State Diagram (P.7)
Updated MR2 Definition (P.18)
Updated Timing Details of Write Leveling Sequence (P.30)
Updated Timing Details of Write Leveling Exit (P.31)
Added Refresh Command (P.50)
Updated MRS Command to Power Down Entry (P.54)
Updated Sync ODT Timing example (P.57)
Updated Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry (P.63)
Updated Sync to async transition during Precharge Power Down (with DLL frozen) (P.63)
Updated AC and DC Logic Input Levels for Single-Ended Signals(P.67)
Added Vref Tolerances (P.68)
Added
Definition of differential ac-
swing and “time above ac-level” (P.69)
Updated Single-ended levels table (P.70)
Updated Cross point voltage for differential input signals. (P.70)
Replaced
Single-Ended Input Slew Rate Definition Table
Input Nominal Slew Rate Definition for Single-Ended Signals Figure
Input Slew Rate for Input Setup Time and Data Setup Time Section
Input Slew Rate for Input Hold Time and Data Hold time Section
with reference to existing definitions of single-ended signals Section (P.102)
Updated Differential Input Slew Rate Definition (P. 71)
Updated IDD Measurement Conditions(P.87/88)
Updated Input/Output Capacitance table (P.85)
Updated DDR3-1333 standard speed pins table (P.90)
Updated Timing Parameters by Speed Bin (P.90)
Updated and reordered Jitter Notes (P.99)
Updated Timing Parameter Notes 11 and 19 for read tRPRE and tRPST
1.0
06/2008
Added IDD currents
Official Release
1.1
08/2008
Added tDIPW data on Timing Parameters on (P. 90 & P. 93)
Add DDR2-1600-CL9/CL10 Item Spec.
1.2
01/2009
Updated IDD4R/IDD4W burst read/write typo (P.83)
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