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| 型号： | NT5CB256M4AN-BF |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA78 |
| 封装： | 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78 |
| 文件页数： | 33/106页 |
| 文件大小： | 2599K |
| 代理商： | NT5CB256M4AN-BF |
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1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
32
REV 1.2
01 / 2009
MPR MR3 Register Definition
MR3
A[2]
MR3
A[1:0]
Function
0
don't care
(0 or 1)
Normal operation, no MPR transaction.
All subsequent Reads will come from DRAM array.
All subsequent Writes will go to DRAM array.
1
See the following table
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
MPR Functional Description
One bit wide logical interface via all DQ pins during READ operation.
Register Read on x4:
DQ [0] drives information from MPR.
DQ [3:1] either drive the same information as DQ [0], or they drive 0.
Register Read on x8:
DQ [0] drives information from MPR.
DQ [7:1] either drive the same information as DQ [0], or they drive 0.
Register Read on x16:
DQL [0] and DQU [0] drive information from MPR.
DQL [7:1] and DQU [7:1] either drive the same information as DQL[0], or they drive 0.
Addressing during for Multi Purpose Register reads for all MPR agents:
BA [2:0]: dont care.
A [1:0]: A [1:0] must be equal to “00”. Data read burst order in nibble is fixed.
A[2]: For BL=8, A[2] must be equal to 0, burst order is fixed to [0,1,2,3,4,5,6,7]; For Burst chop 4 cases, the burst order is switched
on nibble base, A[2]=0, burst order: 0,1,2,3, A[2]=1, burst order: 4,5,6,7. *)
A [9:3]: dont care.
A10/AP: dont care.
A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0
A11, A13: dont care.
Regular interface functionality during register reads:
Support two Burst Ordering which are switched with A2 and A[1:0]=00.
Support of read burst chop (MRS and on-the-fly via A12/BC).
All other address bits (remaining column addresses bits including A10, all bank address bits) will be ignored by the DDR3
SDRAM.
Regular read latencies and AC timings apply.
DLL must be locked prior to MPR READs.
Note *): Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5CB256M8FN-DI | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5CB256M8GN-CG | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16DP-CF | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16FP-DH | 制造商:Nanya Technology Corporation 功能描述:MEMORY |
| NT5CB64M16FP-DII | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
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