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参数资料
| 型号： | NT5CB256M4AN-BF |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA78 |
| 封装： | 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78 |
| 文件页数： | 26/106页 |
| 文件大小： | 2599K |
| 代理商： | NT5CB256M4AN-BF |
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1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
26
REV 1.2
01 / 2009
DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with requires frequency change) during Self-Refresh:
1.
Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must be in high
impedance state before Self-Refresh mode is entered).
2.
Enter Self Refresh Mode, wait until tCKSRE satisfied.
3.
Change frequency, in guidance with “Input clock frequency change” section.
4.
Wait until a stable is available for at least (tCKSRX) at DRAM inputs.
5.
Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from subsequent
DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode
was entered. the ODT signal must continuously be registered LOW until tDLLK timings from subsequent DLL Reset command is
satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was entered, ODT signal can be
registered LOW or HIGH.
6.
Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL.
7.
Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset.
8.
Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be necessary. After
tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or after tDLLK).
9.
Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying command
requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.
CK
T0
Ta 0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf1
Tg0
1)
CMD
CKE
ODT
Th0
tCKSRE
tCKSRX 4)
tXS
tMRD
tDLLK
NOP
SRE 2)
SRX 5)
MRS 6)
MRS 7)
MRS 8)
Valid
ODTLoff
+ 1tck
3)
tMRD
Valid
tCKESR
Time
break
Do not
Care
NOP
Note:
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
1) Starting from Idle State.
2) Enter SR.
3) Change Frequency.
4) Clock must be stable at least tCKSRX.
5) Exit SR.
6) Set DLL-on by MR1 A0="0"
7) Start DLL Reset
8) Any valid command
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PDF描述 |
|---|---|
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| NT5SV8M8DT-7 | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NTC1111-20MHZ | Analog IC |
| NTC1111-SERIES | Analog IC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5CB256M8FN-DI | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5CB256M8GN-CG | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16DP-CF | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16FP-DH | 制造商:Nanya Technology Corporation 功能描述:MEMORY |
| NT5CB64M16FP-DII | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
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