参数资料
型号: NT5CB256M4AN-BF
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: DDR DRAM, PBGA78
封装: 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78
文件页数: 36/106页
文件大小: 2599K
代理商: NT5CB256M4AN-BF
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
35
REV 1.2
01 / 2009
Read Timing Definition
Read Timing; Clock to Data Strobe relationship
Clock to Data Strobe relationship is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK and
.
tDQSCK is the actual position of a rising strobe edge relative to CK and
.
tQSH describes the data strobe high pulse width.
Falling data strobe edge parameters:
tDSL describes the data strobe low pulse width.
Clock to Data Strobe Relationship
Rising Strobe
Region
tDQSK, min
tDQSK, max
tDQSK
CK
DQS
tDQSK
Rising Strobe
Region
tQSH
tQSL
tQH
tDQSQ
Associated
DQ pins
CK
RL Measured
to this point
DQS, DQS
Early Strobe
DQS, DQS
Late Strobe
tLZ(DQS)min
tLZ(DQS)max
tRPRE
tDQSCKmin
tDQSCKmax
tQSH
tQSL
tRPST
tHZ(DQS)min
tHZ(DQS)max
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