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| 型号： | NT5CB256M4AN-BF |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA78 |
| 封装： | 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78 |
| 文件页数： | 14/106页 |
| 文件大小： | 2599K |
| 代理商： | NT5CB256M4AN-BF |
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1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
15
REV 1.2
01 / 2009
CAS Latency
The CAS Latency is defined by MR0 (bit A9~A11) as shown in the MR0 Definition figure. CAS Latency is the delay, in clock cycles,
between the internal Read command and the availability of the first bit of output data. DDR3 SDRAM does not support any half clock
latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL + CL.
Test Mode
The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0 definition figure.
Programming bit A7 to a 1 places the DDR3 SDRAM into a test mode that is only used by the DRAM manufacturer and should not be
used. No operations or functionality is guaranteed if A7=1.
DLL Reset
The DLL Reset bit is self-
clearing, meaning it returns back to the value of 0 after the DLL reset function has been issued. Once the
DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK must be met before any
functions that require the DLL can be used. (i.e. Read commands or ODT synchronous operations)
Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-
down mode. When MR0 (A12=0), or slow-exit, the DLL is
frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be met prior to the next
valid command. When MR0 (A12=1), or fast-exit, the DLL is maintained after entering precharge power-down and upon exiting
power-down requires tXP to be met prior to the next valid command.
Write Recovery
The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to determine tDAL WR
(write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns) and rounding up to the next integer:
WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be equal or larger than tWR(min).
相关PDF资料 |
PDF描述 |
|---|---|
| NT5DS64M8BF-6KI | DDR DRAM, PBGA60 |
| NT5SE8M16DS-6K | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| NT5SV8M8DT-7 | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NTC1111-20MHZ | Analog IC |
| NTC1111-SERIES | Analog IC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5CB256M8FN-DI | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5CB256M8GN-CG | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16DP-CF | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16FP-DH | 制造商:Nanya Technology Corporation 功能描述:MEMORY |
| NT5CB64M16FP-DII | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
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