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| 型号： | NT5CB256M4AN-BF |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM, PBGA78 |
| 封装： | 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78 |
| 文件页数： | 17/106页 |
| 文件大小： | 2599K |
| 代理商： | NT5CB256M4AN-BF |
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1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
18
REV 1.2
01 / 2009
Write leveling
For better signal integrity, DDR3 memory module adopted fly by topology for the commands, addresses, control signals, and clocks.
The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between
clock and strobe at every DRAM on DIMM. It makes difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification.
Therefore, the controller should support write leveling in DDR3 SDRAM to compensate for skew.
Output Disable
The DDR3 SDRAM outputs maybe enable/disabled by MR1 (bit12) as shown in MR1 definition. When this feature is enabled (A12=1)
all output pins (DQs, DQS, DQS#, etc.) are disconnected from the device removing any loading of the output drivers. This feature may
be useful when measuring modules power for example. For normal operation A12 should be set to 0.
TDQS,
TDQS (Termination Data Strobe) is a feature of x8 DDR3 SDRAM that provides additional termination resistance outputs that may be
useful in some system configurations.
TDQS is not supported in x4 and x16 configurations. When enabled via the mode register, the same termination resistance function is
applied to be TDQS/
pins that are applied to the DQS/ pins.
In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function only. The data strobe function
of RDQS is not provided by TDQS.
The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode register, the DM function is not
supported. When the TDQS function is disabled, the DM function is provided and the
pin is not used.
The TDQS function is available in x8 DDR3 SDRAM only and must be disabled via the mode register A11=0 in MR1 for x4 and x16
configurations.
TDQS,
Function Matrix
MR1 (A11)
DM / TDQS
NU / TDQS
0 (TDQS Disabled)
DM
Hi-Z
1 (TDQS Enabled)
TDQS
Note:
1. If TDQS is enabled, the DM function is disabled.
2. When not used, TDQS function can be disabled to save termination power.
3. TDQS function is only available for x8 DRAM and must be disabled for x4 and x16
相关PDF资料 |
PDF描述 |
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| NT5DS64M8BF-6KI | DDR DRAM, PBGA60 |
| NT5SE8M16DS-6K | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| NT5SV8M8DT-7 | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NTC1111-20MHZ | Analog IC |
| NTC1111-SERIES | Analog IC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5CB256M8FN-DI | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5CB256M8GN-CG | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16DP-CF | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16FP-DH | 制造商:Nanya Technology Corporation 功能描述:MEMORY |
| NT5CB64M16FP-DII | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
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