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| 型号： | IDT88P8341BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 31/96页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8341BHGI |
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37
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
5. PERFORMANCE MONITOR AND
DIAGNOSTICS
5.1 Mode of operation
Aperformancemonitor&diagnosticsmoduleisavailable.Theperformance
monitor captures events and accumulates error events and diagnostics data.
Some performance monitor accumulators are associated to a physical port,
some to a LID.
5.2 Counters
All events and diagnostics data are accumulated during an interval defined
by the timebase event. The data accumulated during the previous time period
canbeaccessedbytheindirectaccessscheme.Thecountersareclearedwhen
the timebase expires. All counters are saturating, and will not overflow.
5.2.1 LID associated event counters
Asetof eventcountersisprovidedforeachofthe64LPsontheSPI-3interface
and for each LID to/from the SPI-4 module.
A packet is delineated by an SOP and EOP on the SPI-3 / SPI-4 logical port.
It is defined as “bad” when the packet is tagged with an error.
All packets that are not “bad” are considered “good”.
For more information refer to Table 60 - LID associated event counters
(0x000-0x17F).
5.2.2 Non - LID associated event counters
A set of event counters is provided for the SPI-3 and the SPI-4 physical
interfaces.
Refer to Table 61, Non LID associated event counters (0x00-0x0B) for the
offset in the indirect access space, and for the events recorded.
5.3 Captured events
Two categories of events are captured: LID and non LID associated events.
Ifatleastoneeventiscapturedinoneoftheinterruptindicationregisters,anactive
PMON service request is directed towards the interrupt module.
5.3.1 Non LID associated events
Non LID associated events are captured into the Table 62 - Non LID
associatedinterruptindicationregister(Block_base0x0C00+Register_offset
0x00 to 0x0B). An interrupt is generated if the event is enabled by its enable
flag in the Table 63 - Non LID associated interrupt enable register(Block_base
0x0C00 + Register_offset 0x0D). The interrupt is cleared by writing a logical
onetotheTable62-NonLIDassociatedinterruptindicationregister(Block_base
0x0C00 + Register_offset 0x00 to 0x0B).
5.3.2 LID associated events
Two types of LID associated events are captured. Non critical events are
definedinTable64-LID-associatedinterruptindicationregister(0x0E)andare
associated with the physical interface. Critical events are defined as buffer
overflowswithintheIDT88P8341deviceinTable67,SPI-3toSPI-4criticalLID
interrupt indication registers (register_offset 0x16-0x17).
5.3.2.1 Non critical events
LID associated non critical events are captured in the Table 64, LID-
associated interrupt indication register(0x0E). An interrupt is generated if the
interrupt is enabled by its enable flag in the Table 65, LID-associated interrupt
enableregister(0x0F).Theinterruptindicationisclearedbywritingalogicalone
to the Table 64, LID associated interrupt indication register(0x0E).
When the event is captured, the LID or LP associated with the event is
captured in Table 66, Non-critical LID associated capture table (0x10-0x15).
The table records the latest captured LID or LP.
5.3.2.2 Critical events
Critical events are captured per LID in Table 67, SPI-3 to SPI-4 critical LID
interrupt indication registers (Block_base 0x0C00 + Register_offset 0x16-
0x17) and Table 69, SPI-4 to SPI-3 critical LID interrupt indication registers
(0x1A-0x1B).Aninterruptisgeneratedifenabled bythecorrespondingenable
flag in the Table 68, SPI-3 to SPI-4 critical LID interrupt enable registers (0x18-
0x19)andTable70,SPI-4toSPI-3criticalLIDinterruptenableregisters(0x1C-
0x1D). The indication is cleared by writing a logical one to the Table 67, SPI-
3toSPI-4criticalLIDinterruptindicationregisters(0x16-0x17)orTable69,SPI-
4 to SPI-3 critical LID interrupt indication registers (0x1A-0x1B). Only one kind
of critical event is defined, buffer overflow. Since there are 64 x 2=128 critical
LIDassociatedeventsources,twosourceindicationbitsarecontainedinTable
71, Critical events source indication register (0x1E). The bits are read only. Bit
SPI34_OVR reflects the OR result of all bits in Table 67, SPI-3 to SPI-4 critical
LID interrupt indication registers (0x16-0x17). Bit SPI43_OVR reflects the OR
resultofallbitsinTable69,SPI-4toSPI-3criticalLIDinterruptindicationregisters
(0x1A-0x1B).
5.3.3 Timebase
Asingletimebasemoduleisprovidedinthedevice.Thetimebaseperiodcan
be configured to be internally or externally generated. A snapshot of the
countersistakenwhenthetimebaseexpiresandthecountersarecleared.The
snapshot registers are accessed by an indirect access scheme.
5.3.3.1 Internally generated timebase
The period of the timebase is configured for the device using the register
defined in Table 120, Timebase register (Register_offset 0x01). The configu-
ration specifies the number of master clock (MCLK) cycles required for each
period. For a description of MCLK refer to Chapter 6 Clock generator. The
timebase event is captured by the timebase status in Table 45, Secondary
interrupt status register (0x2D in the direct accessed space).
The internal timebase is generated either by the microprocessor or by a free
running timer input. The selection is made by the TIMER flag in the Table 119,
PMON update control register (Register_offset 0x00). When the time interval
expires, the TIMEBASE pin is asserted for sixteen MCLK cycles.
5.3.3.2 Externally generated timebase
The externally generated timebase signal is applied on the TIMEBASE pin.
A positive edge detector generates the timebase event. The timebase event is
captured by the timebase status in the Table 45 - Secondary interrupt status
register (0x2D in the direct accessed space).
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相关代理商/技术参数 |
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| IDT88P8341BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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