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| 型号： | IDT88P8341BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 73/96页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8341BHGI |
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75
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
TABLE 122 - OCLK AND MCLK FREQUENCY
SELECTENCODING
N_MCLK & N_OCLK[k] Frequency Selects
Frequency
00
pll_oclk / 4
01
pll_oclk / 6
10
pll_oclk / 8
11
pll_oclk / 10
TABLE 121 - CLOCK GENERATOR CONTROL
REGISTER (REGISTER_OFFSET 0x10)
Field
Bits
Length
Initial Value
OCLK0_EN
0
1
0b01
N_OCLK0
2:1
2
0b11
Reserved
3
1
0b0
OCLK1_EN
4
1
0b1
N_OCLK1
6:5
2
0b11
Reserved
7
1
0b0
OCLK2_EN
8
1
0b1
N_OCLK2
10:8
2
0b11
Reserved
11
1
0b0
OCLK3_EN
12
1
0b1
N_OCLK3
14:13
2
0b11
Reserved
16:15
2
0b0
N_MCLK
18:17
2
0b11
Field
Bits
Length
Initial Value
INTERNAL
0
1
0b0
TIMER
1
0b0
MANUAL
2
1
0b0
TABLE 119 - PMON TIMEBASE CONTROL REGIS-
TER (REGISTER_OFFSET 0x00)
9.4.10 Common module block base 0x0900 registers
PMON timebase control register (Block_base
0x0900 + Register_offset 0x00)
AsinglePMONtimebasemoduleisavailableintheIDT88P8344.ThePMON
timebase module directs a timebase event to all PMON modules in the device.
The timebase period can be internally or externally generated. The selection
ismadebytheINTERNALflaginthePMONupdatecontrolregister. Asnapshot
ofthecountersistakenwhenthetimebaseexpiresandthecountersarecleared.
ThePMONupdatecontrolregisterisatcommonmodule0x8000+Block_base
0x0900 + Register_offset 0x00 = 0x8900 and has read and write access.
INTERNAL
Selectsbetweeninternalorexternaltimebasesforperfor-
mance monitoring. The internal timebase is either generated by the internal
processor or by a free running timer. The selection is made by the TIMER flag
in the PMON update control register. When the time interval expires, the
TIMEBASE pin is asserted for sixteen MCLK cycles. The timebase event is
captured by the timebase status in the support interrupt status register.
0= External timebase from the TIMEBASE pin is selected. The externally
generated timebase signal is applied to the TIMEBASE pin. A positive edge
detector generates the timebase event.
1=Internaltimebaseisselected.Whenthetimeintervalexpires,theTIMEBASE
pin is driven high for sixteen MCLK cycles.
TIMER Selects between the internal free-running timebase or a micropro-
cessor-controlledwritetogeneratethetimebaseevent.TheTIMERfieldisvalid
only when the INTERNAL field is a logic one.
0=Selects the microprocessor generated timebase
1=Selects the internal free-running timebase
MANUAL
Themicroprocessorgeneratesaninternaltimebaseevent
by a write access with a logical one to the MANUAL flag in the PMON Update
Control Register if the microprocessor timebase is selected. The MANUAL bit
is self-clearing. The MANUAL field is only valid if the TIMER field is a logic zero.
0=No operation
1=A timebase event is generated
Timebase register (Block_base 0x0900 +
Register_offset 0x01)
TABLE 120 - TIMEBASE REGISTER
(REGISTER_OFFSET 0x01)
Field
Bits
Length
Initial Value
PERIOD
26:0
27
0x4A2 8600
The timebase register is at Block_base 0x0900 + Register_offset 0x01 and
has read and write access.
Thetimebaseperiodforfree-runningtimersisconfiguredbythePERIODfield
inthetimebaseregister.ThePERIODfieldspecifiesthenumberofMCLKclock
cycles required for a single event. The PERIOD field is only valid if both the
INTERNAL and TIMER fields are a logic one.
Clock generator control register (Block_base
0x0900 + Register_offset 0x010)
The clock generator control register is at common module Block_base
0x0900 + Register_offset 0x010.
The clock generator provides four clock outputs on the OCLK[3:0] pins,
MCLK for internal use, and SPI-4 data and FIFO status channel egress clocks.
TheOCLK[3:0]clockfrequenciescanbeselectedindependentlyofeachother.
OCLK[3:0] outputs can be used as SPI-3 clock sources. The OCLK[3:0] pins
are separately enabled by setting each associated enable flag in Table 121 -
Clock generator control register (Register_offset 0x10). When an OCLK[3:0]
output is not enabled, it is in a logic low state. MCLK is the internal processing
clock, and is always enabled. Refer to Table 122 - OCLK and MCLK frequency
select encoding, for selecting the frequencies of MCLK and OCLKs.
Duringeitherahardwareorasoftwarereset,theOCLK[3:0]pinsarealllogic
low.Immediatelyfollowingreset,allOCLK[3:0]outputsareactivewiththeoutput
frequencydefinedbypll_oclkdividedbytheinitialvalueintheTable121-Clock
generator control register (Block_base 0x0900 + Register_offset 0x10).
Theclockgeneratorcontrolregisteratindirectaddress0x8910hasreadand
write access. The clock generator control register is used to set the frequency
of MCLK and the OCLK outputs, as well as to enable the OCLK outputs. Note
that divider values should be chosen so that OCLK[3:0] and MCLK are within
theirspecifiedoperatingrangeprovidedinTable136,OCLK[3:0]clockoutputs
and MCLK internal clock.
OCLK[k]_EN
Used for enabling the kth OCLK output
0=OCLK[k] is not enabled and OCLK[k] is at a logic zero
1=OCLK[k] is enabled and active
N_OCLK[k] [1:0] Select the OCLK[k] frequency according to Table 122-
OCLK and MCLK frequency select encoding.
N_MCLK[k] Select the MCLK frequency according to Table 122-OCLK
and MCLK frequency select encoding.
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相关代理商/技术参数 |
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| IDT88P8341BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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