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IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
I_BUS_ERR_EN
SPI-4 ingress bus error interrupt indication enable.
0=Disable bus error interrupt
1=Enable bus error interrupt
SPI4_INACTIVE_TRANSFER_EN SPI-4ingressinactivetransferinter-
rupt indication enable.
0=Disable inactive transfer interrupt
1=Enable inactive transfer interrupt
DCLK_UN_EN SPI-4 ingress data clock has transitioned from available
to an unavailable condition interrupt indication enable.
0=Disable unavailable interrupt
1=Enable unavailable interrupt
E_DIP_ERR_EN
SPI-4 egress DIP-2 error interrupt indication enable
on the SPI-4 egress status channel.
0=Disable DIP-2 error interrupt
1=Enable DIP-2 error interrupt
E_SYNCH_EN SPI-4 egress status channel has transitioned from out of
synchronization to in synchronization condition interrupt indication enable.
0=Disable synchronization interrupt
1=Enable synchronization interrupt
SCLK_UN_EN SPI-4egressstatusclockhastransitionedfromavailable
to an unavailable condition interrupt indication enable. SCLK_UN_EN should
be written as a zero if using a SPI-4 egress LVTTL status clock that is less than
one-half of the MCLK frequency. The SCLK_UN_I interrupt indication is not
usable in this case.
0=Disable unavailable interrupt
1=Enable unavailable interrupt
Module status register (0x24 in the direct ac-
cessed space)
Field
Bits
Length
Initial Value
SPI-34_CAPTURE
0
1
0
SPI-43_CAPTURE
1
0
SPI-34_INSERT
2
1
0
SPI-43_INSERT
3
1
0
PMON
4
1
0
Reserved
7:5
3
0
TABLE 42 - MODULE STATUS REGISTER (0x24 IN
THEDIRECTACCESSEDSPACE)
TheModuleStatusregister(0x24inthedirectaccessedspace)hasreadand
write access, and interrupt status fields are cleared by a microprocessor write
cycle, where a logical one must be written to clear the field(s) targeted, except
for the PMON field, which can not be cleared.
The Module Status register is a secondary interrupt status register and can
only be active if the corresponding field is active in the primary interrupt status
register (Direct access register 0x2C).
SPI-34_CAPTURE
SPI-3 ingress to SPI-4 egress capture event inter-
ruptindication.
0=No capture event
1=Buffer is ready for reading by the microprocessor
SPI-43_CAPTURE
SPI-4ingresstoSPI-3egresscaptureeventinterrupt
indication.
0=No capture event
1=Buffer is ready for reading by the microprocessor
SPI-34_INSERT SPI-3 ingress to SPI-4 egress insert event interrupt
indication.
0=No insert event
1=Buffer is ready for writing by the microprocessor
SPI-43_INSERT
SPI-4 ingress to SPI-3 egress insert event interrupt
indication.
0=No insert event
1=Buffer is ready for writing by the microprocessor
PMON PerformanceMonitoreventinterruptindication.Writingtothisfieldhas
noeffect.
0=No PMON event
1=PMON event is ready for reading by the microprocessor
Module enable register (0x28 in the direct ac-
cessed space)
Field
Bits
Length
Initial Value
SPI-34 CAPTURE_EN
0
1
0
SPI-43 CAPTURE_EN
1
0
SPI-34 INSERT_EN
2
1
0
SPI-43 INSERT_EN
3
1
0
PMON_EN
4
1
0
Reserved
7:5
3
0
TABLE 43 - MODULE ENABLE REGISTER (0x28 IN
THEDIRECTACCESSEDSPACE)
The Module Enable register (0x28 in the direct accessed space) has read
and write access.
SPI-34_CAPTURE_EN
SPI-3 ingress to SPI-4 egress capture event
interrupt enable.
0=Disable capture interrupt
1=Enable capture interrupt
SPI-43_CAPTURE_EN
SPI-4 ingress to SPI-3 egress capture event
interrupt enable.
0=Disable capture interrupt
1=Enable capture interrupt
SPI-34_INSERT_EN
SPI-3ingresstoSPI-4egressinserteventinterrupt
enable.
0=Disable insert interrupt
1=Enable insert interrupt
SPI-43_INSERT_EN
SPI-4 ingress to SPI-3 egress insert event
interrupt enable.
0=Disable insert interrupt
1=Enable insert interrupt
PMON_EN
Performance Monitor event interrupt enable.
0=Disable PMON interrupt
1=Enable PMON interrupt