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| 型号： | IDT88P8341BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 36/96页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8341BHGI |
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41
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
2) Configure the clock generator as follows:
a) Configure the value for the MCLK divider, OCLK dividers and
enablesintheClockGeneratorControlRegister(refertoTable121,
Clock generator control register (Register_offset 0x10)).
b) Configure the values for I_LOW and E_LOW (refer to Table 89, SPI-
4 ingress configuration register (0x00) and Table 104, SPI-4
egress configuration register_0 (Register_offset 0x00).
3) Load status channel firmware. See section 8.2.5 for details.
4) Configure all PFPs as follows:
a)TheNR_LIDfieldsmustbeconfiguredfirst.DonotchangetheNR_LID
fields once configured after reset. The NR_LID fields are in the Table
76, SPI-3 to SPI-4 PFP register (register_offset 0x00) and the
Table 83, SPI-4 to SPI-3 PFP register (0x00).
b) There are four sets of port descriptor tables: The Table 73, SPI-4
egressportdescriptortable(64entries),theTable75,SPI-3ingressport
descriptor table (Block_base 0x1200), the Table 80, SPI-3 egress port
descriptor table (64 entries), and the Table 82, SPI-4 ingress port
descriptor tables (64 entries). Configure the M (SPI-4 egress),
MAX_BURST_S, MAX_BURST_H, DIRECTION (SPI-4 egress),
FREE_SEGMENT, MAX_BURST, DIRECTION (SPI-3 egress), M
(SPI-4 ingress), FREE_SEGMENT_S, and FREE_SEGMENT_H
parametersoftheportdescriptortablesforeachLIDtobeactivated.The
total buffer segment assignment should not exceed the available buffer
segment pool capacity of 508 segments per PFP.
5) Configure the Table 54- SPI-3 egress LID to LP map.
6) Configure the Table 49 - SPI-3 ingress LP to LID map.
7) The SPI-4 Calendar tables must be configured before the SPI-4 mapping
tables are configured. Do not change the SPI-4 calendar tables once they are
configured. In LVDS status mode, ensure that the value of (CAL_LEN+1) *
(M+1) is at least 4.
a) Configure the SPI-4 ingress calendar or calendars (refer to Table 87,
SPI-4 ingress calendar_0 (256 entries) and Table 88, SPI-4 ingress
calendar_1 (256 entries)).
b)ConfiguretheSPI-4egresscalendarorcalendars(refertoTable102,
SPI-4 egress calendar_0 (256 locations) and Table 103, SPI-4
egress calendar_1 (256 locations)).
8) Configure the Table 101, SPI-4 egress LID to LP map (256 entries).
9) Configure the Table 86, SPI-4 ingress LP to LID (256 entries, one per LP).
10) Configure the SPI-4 physical interface. The Table 89, SPI-4 ingress
configurationregister(0x00),Table104,SPI-4egressconfigurationregister_0
(Register_offset 0x00), and Table 105, SPI-4 egress configuration register_1
(Register_offset 0x01) must be configured before enabling the SPI-4 physical
interface. OncetheSPI-4interfaceisenabled,theSPI-4interfaceconfiguration
registers can not be changed unless the chip is reset. Individual LIDs can still
be enabled or disabled, within the bounds set by NR_LID.
11) Configure the SPI-3 physical interface. The Table75,SPI-3ingressport
descriptor table (Block_base 0x1200) must be configured before enabling the
SPI-3 physical interface. Once the SPI-3 interface is enabled, Table 80, SPI-
3 egress port descriptor table (64 entries) can not be changed unless the chip
is reset. Individual LIDs can still be enabled or disabled without a chip reset,
within the bounds set by NR_LID.
12) Enable the SPI-3 physical interface. Set the enable bit per LID in Table
46, SPI-3 ingress LP to LID map and Table 54, SPI-3 egress LID to LP map.
13) Enable the SPI-4 physical interface. Set the enable bit per LID in Table
82, SPI-4 ingress LP to LID map (256 entries, one per LP) and Table 101, SPI-
4 egress LID to LP map (256 entries).
Note: Sufficient edge transitions on the bus are required to cause a change
in the TAP value. Therefore, the adjacent device should send training for at
least 100ms in the end of the initialization sequence & before starting to send
data. The bit alignment will select the best tap for each lane.
8.2.2 Logical Port activation and deactivation
Dynamically deactivate a logical port
The procedure for deactivating a logical port is outlined as follows:
1) Configure the enable bit of the ingress LP to LID map to “disabled”.
2) Configure the egress data DIRECTION field in Table 73, SPI-4 egress
portdescriptortable(64entries)orTable80,SPI-3egressportdescriptortable
(64 entries) to “discard”.
3) Wait at least 0.1ms for the flush of the remaining data in the queue.
4) Change M to 0 for the LP.
Dynamically activate a logical port
The procedure for activating a logical port is outlined as follows:
1) Make sure the LID is inactive.
2) Configure M for the desired LID.
3) Configure the egress LID to LP map, then enable the LID.
4) Configure the egress data direction for the LID.
5) Configure the ingress LP to LID map, then enable the LP.
8.2.3 Buffer segment modification
Modification of the buffer segment allocation for a LID
The buffer segment allocation can be changed while the corresponding LP
is disabled. The amount of buffering available for a LID can be decreased or
itcanbeincreasedifmorebuffersegmentsareavailableforuse.Theprocedure
for changing the buffer segment allocation for a LID is outlined as follows:
1) Disable the LP corresponding to the LID to undergo buffer segment
modification.
2)Discardthefragments,byconfiguringtheDIRECTIONfieldforDISCARD
for the LID.
3) Wait at least 0.1ms for the buffer to empty.
4) Change M to 0 for the LID.
5) Configure the new M value for the LID.
6) Configure the DIRECTION field for the LID to restore data flow.
7) Enable the LP corresponding to the LID that underwent buffer segment
modification.
8.2.4 Manual SPI-4 ingress LVDS bit alignment
The procedure for manually adjusting the SPI-4 ingress LVDS bit alignment
is outlined. It is recommended to use automatic alignment in most cases.
1)ConfiguretheFORCEbitfromTable99,SPI-4 ingressbitalignmentcontrol
register (register_offset 0x11). This puts the SPI-4 ingress under manual
control.
2) Configure the SPI-4 ingress data lane to be measured for clock-data
alignment in Table 111, SPI-4
ingress lane measure register
(register_offset 0x01), LANE field.
3) Wait for the eye measurement to complete in Table 111, SPI-4 ingress
lane measure register (register_offset 0x01), MEASURE_busy field.
4) Read the eye pattern counter in Table 112, SPI-4 ingress bit alignment
counter register (0x02 to 0x0B).
5) Calculate the proper value.
6) Configure the appropriate phase tap in Table 113, SPI-4 ingress manual
alignment phase/result register (0x0C to 0x1F).
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| IDT88P8341BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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