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| 型号： | IDT88P8341BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/96页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8341BHGI |
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13
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
3. EXTERNAL INTERFACES
The external interfaces provided on the IDT88P8341 device are two SPI-
3 interfaces, one SPI-4 interface, a serial or parallel microprocessor interface,
aJTAGinterface,andasetofGPIOpins.Eachoftheinterfacesisdefinedinthe
relevant standard.
The following information contains a set of the highlights of the features
supportedfromtherelevantstandards,andadescriptionofadditionalfeatures
implementedtoenhancetheusabilityoftheseinterfacesforthesystemarchitect.
3.1 SPI-3
RefertoOIFSPI-3document(see13.Glossaryforareference)forfulldetails
oftheimplementationagreement.
- Two instantiations of SPI-3 interface; each interface independently
configurable
- Device supports a 8-bit and 32-bit data bus structure.
- Clock rate is minimum 19.44 to maximum 133 MHz
- Link, single port PHY, and single device multi port PHY modes supported
- Byte level and packet level transfer control mechanisms supported
FourDTPAsignalssupported,mappedtoLPaddresses0–3,forSTPA
in byte-level mode
Eight ADR signals supported for PTPA in packet-level mode
-Addressrange0to255withsupportfor64simultaneouslyactivelogicalports
- Fragment length (section) configurable from 16 to 256 bytes in 16 byte
multiples
- Configurable standard and non-standard bit ordering
SPI-3 implementation features
The following are implemented per SPI-3 interface, and there are two
instantiations per device.
- Link / PHY layer device
- Packet / byte level FIFO status information
- Physical port enable
- Width of data bus (32 bit or 8 bit)
- Parity selection (odd or even)
- Enable parity check
3.1.1 SPI-3 ingress
The following are implemented per SPI-3 interface, and there are 4
instantiations per device.
- SPI-3 LP to Link Identifier (LID) map
- 256 entries, one per SPI-3 LP address
- LP enable control
- Only 64 of these entries are to be in the active state simultaneously
Backpressure enable
- Link mode only
- Enables the assertion of the I_ENB when at least one active LID can not
acceptdata
-Ifnotenabled,theI_ENBsignalwillneverbeassertedinLinkmode,possibly
leading to fragments being discarded.
Minimum packet length
- Packets shorter than the minimum length will be optionally counted in the
short packet counter.
- Range 0 – 255 in 1 byte increments
Maximum packet length
- Packets longer than the maximum length will be optionally counted in the
long packet counter.
- Range 0 – 16,383 in 1 byte increments
Backpressure threshold
- Number of free segments allocated below which backpressure will be
triggered for the LP
SPI-3 ingress interface
MultipleindependentdatastreamscanbetransmittedoverthephysicalSPI-
3port.EachofthosedatastreamsisidentifiedbyaSPI-3logicalport(LP).Data
from a transfer on a SPI-3 logical port and the associated descriptor fields are
synchronized to the configurable internal buffer segment pool.
Normal operation
Refer to [13. Glossary] for details about the SPI-3 interface.
A SPI-3 interface ( a physical port ) is enabled by the SPI-3_ENABLE flag
in the SPI-3 configuration register. A disabled interface tri-states all output
pins and does not respond to any input signals.
The interface is configured in PHY or Link layer mode by the LINK flag
in the SPI-3 general configuration register.
TheinterfacesupportsaSPI-3logicalportnumberrange[0..255],notethat
at most 64 logical ports can be configured.
The SPI-3 interface supports data transport over either a 32 bit data
interface or over one single 8 bit interface (data[7:0] ) only. The selection
isdefinedbytheBUSWIDTHflagintheSPI-3generalconfigurationregister.
The SPI-3 interface is configured in byte mode or packet mode by the
PACKET flag in the SPI-3 general configuration register.
The SPI-3 interface supports over-clocking.
Parity checking over data[31:0] is enabled by the PARITY_EN flag in the
Table50,SPI-3generalconfigurationregister(register_offset=0x00).The
parity type is defined by the EVEN_PARITY flag. Parity check results over
the in-band port address and the data of a transfer are forwarded towards
the packet fragment processor.
SPI Exchange supports zero clock interval spacing between transfers.
SPI-3 ingress interface errors
Given an I_FCLK within specification, the SPI-3 will not dead lock due to any
combinationorsequenceontheSPI-3interface.TheSPIExchangedetectsfor
incorrectSOP/EOPsequencesonalogicalport.Thefollowingsequencesare
detected:
SuccessiveSOP(SOP-SOPsequenceratherthanSOP–EOP–SOP-EOP)
SuccessiveEOP(EOP-EOPsequenceratherthanSOP–EOP–SOP-EOP)
Detection of an illegal sequence results in the generation of an SPI-3 illegal
SOP sequence event or SPI-3 illegal EOP sequence even generated. The
eventisassociatedtothephysicalport.TheeventisdirectedtowardsthePMON
& DIAG module.
A clock available process detects a positive I_FCLK within a 64 MCLK clock
cycle period. The result of this process is reported in the I_FCLK_AV flag in the
Table 52 SPI-3 ingress fill level register (Block_base 0x0200 + Register_offset
0x02).
Astatuschangefromtheclockavailablestatustotheclocknotavailablestatus
generates a maskable SPI-3 ingress clock unavailable interrupt indication,
SPI3_ICLK_UN, in Table 62-Non LID associated interrupt indication register
(Block_Base 0x0C00 + Register_offset 0x0C).
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相关代理商/技术参数 |
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| IDT88P8341BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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