参数资料
型号: IDT88P8341BHGI
厂商: IDT, Integrated Device Technology Inc
文件页数: 49/96页
文件大小: 0K
描述: IC SPI3-SPI4 EXCHANGE 820-PBGA
标准包装: 24
系列: *
其它名称: 88P8341BHGI
53
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Theprimaryinterruptstatusregister(0x2Cinthedirectaccessedspace)has
read-only access. The interrupts for the primary interrupt status register must
be acknowledged by servicing the corresponding secondary interrupt status
registers.
MODULE_A
When active, the MODULE_A field is responsible for
allowinganinterruptintheModuleStatusRegister(secondaryinterruptregister
0x24).
0=No MODULE_A interrupt active
1=MODULE_A interrupt is active
SPI-4 When active, the SPI-4 field is responsible for allowing an interrupt
in the SPI-4 status register (secondary interrupt register 0x22).
0=No SPI-4 interrupt active
1=SPI-4 interrupt is active
SECONDARY
When active, the SECONDARY field is responsible for
allowing an interrupt in the Secondary Interrupt Status Register (secondary
interrupt register 0x2D).
0=No SECONDARY interrupt active
1=SECONDARY interrupt is active
Secondary interrupt status register (0x2D in the
direct accessed space)
Primary interrupt status register (0x2C in the
direct accessed space)
INDIRECT_ACCESS
Indirectaccesscompletioninterruptindication.
0=No indirect access event
1=Indirect access has completed
Primary interrupt enable register (0x2E in the
direct accessed space)
Field
Bits
Length
Initial Value
MODULE_A
0
1
0
Reserved
1
0
Reserved
2
1
0
Reserved
3
1
0
SPI-4
4
1
0
SECONDARY
5
1
0
Reserved
7:6
2
0
TABLE 44 - PRIMARY INTERRUPT STATUS REGIS-
TER (0x2C IN THE DIRECT ACCESSED SPACE)
Field
Bits
Length
Initial Value
TIME_BASE
0
1
0
INDIRECT_ACCESS
1
0
Reserved
7:2
6
0
TABLE 45 - SECONDARY INTERRUPT STATUS
REGISTER (0x2D IN THE DIRECT ACCESSED SPACE)
The primary interrupt enable register (0x2E in the direct accessed space)
has read and write access.
ThePrimaryInterruptEnableRegisterisusedtobitwiseenabletheinterrupts
in the Primary Interrupt Status Register.
MODULE_A_EN
MODULE_A interrupt enable.
0=Disable MODULE_A interrupt
1=Enable MODULE_A interrupt
SPI-4_EN
SPI-4 interrupt enable.
0=Disable SPI-4 interrupt
1=Enable SPI-4 interrupt
SECONDARY_EN
SECONDARY interrupt enable.
0=Disable SECONDARY interrupt
1=Enable SECONDARY interrupt
Secondary interrupt enable register (0x2F in the
direct accessed space)
The secondary interrupt status register (0x2D in the direct accessed space)
has read and write access.
Thesecondaryinterruptstatusregisterhasreadaccess,andInterruptstatus
fields are cleared by a microprocessor write cycle, where a logical one must
be written to clear the field(s) targeted.
Thesecondaryinterruptstatusregisterisasecondaryinterruptstatusregister
and can only be active if the SECONDARY_EN field is active in the primary
interrupt enable register (Direct 0x2C).
TIME_BASE
Time base expiration interrupt indication.
0=No time base event
1=Time base has expired
Field
Bits
Length
Initial Value
MODULE_A_EN
0
1
0
Reserved
1
0
Reserved
2
1
0
Reserved
3
1
0
SPI4_EN
4
1
0
SECONDARY_EN
5
1
0
Reserved
7:6
2
0
TABLE 46 - PRIMARY INTERRUPT ENABLE REGIS-
TER (0x2E IN THE DIRECT ACCESSED SPACE)
Field
Bits
Length
Initial Value
TIME_BASE_EN
0
1
0
INDIRECT_ACCESS_EN
1
0
Reserved
7:2
6
0
TABLE 47 - SECONDARY INTERRUPT ENABLE
REGISTER(0x2FINTHEDIRECTACCESSEDSPACE)
Thesecondaryinterruptenableregister(0x2Finthedirectaccessedspace)
has read and write access.
The secondary interrupt enable register is used to bitwise enable the
interrupts in the secondary interrupt enable register.
TIME_BASE_EN
Time base expiration interrupt enable.
0=Disable time base event interrupt
1=Enable time base event interrupt
INDIRECT_ACCESS_EN
Indirectaccesscompletioninterruptenable.
0= Disable indirect access completion event interrupt
1=Enable indirect access completion event interrupt
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