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参数资料
型号： IPR-FFT
厂商： Altera
文件页数： 12/70页
文件大小： 0K
描述： IP FFT/IFFT RENEW
标准包装： 1
系列： *
类型： MegaCore
功能： 快速傅里叶变换处理器
许可证： 续用许可证
1–8
Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Stratix III Devices
Table 1–10 lists the streaming data flow performance, using the 4 multipliers/2 adders
complex multiplier structure, for data and twiddle width 16, for Stratix III
(EP3SE50F780C2) devices.
Table 1–9. Performance with the Streaming Data Flow Engine Architecture—Stratix III Devices
Points
256
1024
4096
Combinational
ALUTs
2094
2480
2357
Logic
Registers
3715
4458
4545
Memory
(Bits)
39168
155904
622848
Memory
(M9K)
20
20
76
18 × 18
Blocks
12
12
12
f MAX
(MHz)
442
413
388
Clock
Cycle
Count
256
10024
4096
Transform
Time ( ? s)
0.58
2.48
10.57
Table 1–11 lists the variable streaming data flow performance, with in order inputs
and bit-reversed outputs, for width 16 (32 for floating point), for Stratix III
(EP3SE50F780C2) devices.
1
The variable streaming with fixed-point number representation uses natural word
growth, therefore the multiplier requirement is larger compared with the equivalent
streaming FFT with the same number of points.
If you want to significantly reduce M9K memory utilization, set a lower f MAX target.
Table 1–10. Performance with the Variable Streaming Data Flow Engine Architecture—Stratix III Devices
Point Type
Fixed
Fixed
Fixed
Floating
Floating
Points
256
1024
4096
256
1024
Combinational
ALUTs
2511
3476
4480
14059
18019
Logic
Registers
3927
5244
6628
13424
16560
Memory
(Bits)
10239
42218
170639
34728
140750
Memory
(M9K)
16
23
42
64
95
18 × 18
Blocks
20
28
36
48
64
f MAX
(MHz)
341
323
320
303
286
Clock
Cycle
Count
256
1024
4096
256
1024
Transform
Time ( ? s)
0.75
3.17
12.8
0.84
3.58
Floating
(1)
4096
22026
19717
568579
150
80
286
4096
14.33
Note to Table 1–11 :
(1) EP3SL70F780C2 device.
Table 1–12 lists resource usage with buffered burst data flow architecture, using the
4 multipliers/2 adders complex multiplier structure, for data and twiddle width 16,
for Stratix III (EP3SE50F780C2) devices.
Table 1–11. Resource Usage with Buffered Burst Data Flow Architecture—Stratix III Devices (Part 1 of 2)
Points
256
1024
4096
256
Number of
Engines (1)
1
1
1
2
Combinational
ALUTs
1952
1989
2031
3261
Logic
Registers
3586
3784
3968
5577
Memory
(Bits)
30976
123136
491776
30976
Memory
(M9K)
16
16
60
31
18 × 18
Blocks
12
12
12
24
f MAX
(MHz)
408
390
382
365
FFT MegaCore Function
User Guide
November 2013 Altera Corporation
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