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参数资料
| 型号： | IPR-FFT |
| 厂商： | Altera |
| 文件页数： | 7/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 续用许可证 |
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Chapter 1: About This MegaCore Function
General Description
1–3
■
■
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
DSP Builder ready
f For more information about Avalon-ST interfaces, refer to the Avalon Interface
Specifications .
General Description
The FFT MegaCore function is a high performance, highly-parameterizable Fast
Fourier transform (FFT) processor. The FFT MegaCore function implements a
complex FFT or inverse FFT (IFFT) for high-performance applications.
The FFT MegaCore function implements the following architectures:
■
■
Fixed transform size architecture
Variable streaming architecture
Fixed Transform Size Architecture
The fixed transform architecture FFT implements a radix-2/4 decimation-in-
frequency (DIF) FFT fixed-transform size algorithm for transform lengths of 2 m where
6 ? m ?? 16. This architecture uses block-floating point representations to achieve the
best trade-off between maximum signal-to-noise ratio (SNR) and minimum size
requirements.
The fixed transform architecture accepts as an input a two’s complement format
complex data vector of length N, where N is the desired transform length in natural
order; the function outputs the transform-domain complex vector in natural order. An
accumulated block exponent is output to indicate any data scaling that has occurred
during the transform to maintain precision and maximize the internal signal-to-noise
ratio. Transform direction is specifiable on a per-block basis via an input port.
Variable Streaming Architecture
The variable streaming architecture FFT implements two different types of
architecture. The variable streaming FFT variations implement either a radix-2 2 single
delay feedback architecture, using a fixed-point representation, or a mixed radix-4/2
architecture, using a single precision floating point representation. After you select
your architecture type, you can configure your FFT variation during runtime to
perform the FFT algorithm for transform lengths of 2 m where 3 ?? m ?? 18.
The fixed-point representation grows the data widths naturally from input through to
output thereby maintaining a high SNR at the output. The single precision floating
point representation allows a large dynamic range of values to be represented while
maintaining a high SNR at the output.
f For more information about radix-2 2 single delay feedback architecture, refer to S. He
and M. Torkelson, A New Approach to Pipeline FFT Processor, Department of Applied
Electronics, Lund University, IPPS 1996 .
November 2013
Altera Corporation
FFT MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-FIR | 功能描述:开发软件 FIR Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPRI2CCMFP001 | 制造商:System Level Solutions (SLS) 功能描述:IP CORE, FPGA, I2C CNTLR, FOR CYCLONE, STRATIX, Software Application:IP CORE, In |
| IPR-ILKN/100G | 功能描述:开发软件 Interlaken - 100G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-ILKN/50G | 功能描述:开发软件 Interlaken - 50G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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