参数资料
型号: IPR-FFT
厂商: Altera
文件页数: 64/70页
文件大小: 0K
描述: IP FFT/IFFT RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: 快速傅里叶变换处理器
许可证: 续用许可证
A–4
Appendix A: Block Floating Point Scaling
Achieving Unity Gain in an IFFT+FFT Pair
Because this example has 27 bits of full scale resolution and 16 bits of output
resolution, choose the bottom 16 bits to maintain unity gain relative to the input
signal. Choosing the LSBs is not the only solution or the correct one for all cases. The
choice depends on which signal levels are important. One way to empirically select
the proper range is by simulating test cases that implement expected system data. The
output of the simulations must tell what range of bits to use as the output register. If
the full scale data is not used (or just the MSBs), you must saturate the data to avoid
wraparound problems.
Figure A–1. Scaling of Input Data Sample = 0x5000
Achieving Unity Gain in an IFFT+FFT Pair
Given sufficiently high precision, such as with floating-point arithmetic, it is
theoretically possible to obtain unity gain when an IFFT and FFT are cascaded.
However, in BFP arithmetic, special attention must be paid to the exponent values of
the IFFT/FFT blocks to achieve the unity gain. This section explains the steps required
to derive a unity gain output from an Altera IFFT/FFT MegaCore pair, using BFP
arithmetic.
Because BFP arithmetic does not provide an input for the exponent, you must keep
track of the exponent from the IFFT block if you are feeding the output to the FFT
block immediately thereafter and divide by N at the end to acquire the original signal
magnitude.
November 2013 Altera Corporation
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