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| 型号： | IPR-FFT |
| 厂商： | Altera |
| 文件页数： | 57/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 续用许可证 |
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Chapter 3: Functional Description
Parameters
Table 3–3. Parameters (Part 2 of 3)
3–15
Parameter
Structure
Implement Multipliers in
DSP Resource Optimization
Global clock enable
Twiddle ROM Distribution
Value
3 Mults/5 Adders
4 Mults/2 Adders
DSP Blocks/Logic Cells
Logic Cells Only
DSP Blocks Only
On or Off
On or Off
100% M4K to 100%
M512 or 100% M9K to
100% MLAB
Description
You can implement the complex multiplier structure with four
real multipliers and two adders/subtracters, or three
multipliers, five adders, and some additional delay elements.
The 4 Mults/2 Adders structure uses the DSP block structures
to minimize logic usage, and maximize the DSP block usage.
This option may also improve the push button f MAX . The
5 Mults/3 Adders structure requires fewer DSP blocks, but
more LEs to implement. It may also produce a design with a
lower f MAX . Not available for variable streaming architecture or
in Arria V, Cyclone V, and Stratix V devices.
Each real multiplication can be implemented in DSP blocks or
LEs only, or using a combination of both. If you use a
combination of DSP blocks and LEs, the FFT MegaCore
function automatically extends the DSP block 18 × 18
multiplier resources with LEs as needed. Not available for
variable streaming architecture or in Arria V, Cyclone V, and
Stratix V devices.
This option is available in Stratix V devices for all architectures
and representations. You can turn on this option to implement
the complex multiplier structure using Stratix V DSP block
complex 18 × 25 multiplication mode or complex 27 × 27
multiplication mode for better DSP resource utilization, at the
possible expense of speed. In the variable streaming
architecture using the floating point representation, this option
implements the complex multiplier structure using Stratix V
DSP block complex 27 × 27 multiplication mode at the possible
expense of accuracy.
Turn on if you want to add a global clock enable to your design.
High-throughput FFT parameterizations can require multiple
shallow ROMs for twiddle factor storage. If your target device
family supports M512 RAM blocks (or MLAB blocks in
Stratix III, Stratix IV, and Stratix V devices), you can choose to
distribute the ROM storage requirement between M4K (M9K in
Stratix III and Stratix IV devices) RAM and M512 (MLAB) RAM
blocks by adjusting the slider bar. Set the slider bar to the far
left to implement the ROM storage completely in M4K (M9K)
RAM blocks; set the slider bar to the far right to implement the
ROM completely in M512 (MLAB) RAM blocks. In Stratix V
devices, replace M4K (M9K) with M20K memory blocks.
Implementing twiddle ROM in M512 (MLAB) RAM blocks can
lead to a more efficient device internal memory bit usage.
Alternatively, this option can be used to conserve M4K (M9K)
RAM blocks used for the storage of FFT data or other storage
requirements in your system.
Not available for variable streaming architecture or in the
Cyclone series of device families.
November 2013
Altera Corporation
FFT MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-FIR | 功能描述:开发软件 FIR Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPRI2CCMFP001 | 制造商:System Level Solutions (SLS) 功能描述:IP CORE, FPGA, I2C CNTLR, FOR CYCLONE, STRATIX, Software Application:IP CORE, In |
| IPR-ILKN/100G | 功能描述:开发软件 Interlaken - 100G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-ILKN/50G | 功能描述:开发软件 Interlaken - 50G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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