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| 型号： | IPR-FFT |
| 厂商： | Altera |
| 文件页数： | 8/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 续用许可证 |
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1–4
Chapter 1: About This MegaCore Function
MegaCore Verification
The order of the input data vector of size N can be natural, bit- or digit-reversed, or
– N /2 to N /2 (DC-centered). The fixed-point representation supports a natural,
bit-reversed, or DC-centered order and the floating point representation supports a
natural, digit-reversed, or DC-centered order. The architecture outputs the
transform-domain complex vector in natural, bit-reversed, or digit-reversed order.
The transform direction is specifiable on a per-block basis using an input port.
MegaCore Verification
Before releasing a version of the FFT MegaCore function, Altera runs comprehensive
regression tests to verify its quality and correctness.
Custom variations of the FFT MegaCore function are generated to exercise its various
parameter options, and the resulting simulation models are thoroughly simulated
with the results verified against master simulation models.
Performance and Resource Utilization
Performance varies depending on the FFT engine architecture and I/O data flow. All
data represents the geometric mean of a three seed Quartus II synthesis sweep.
1
Cyclone III devices use combinational look-up tables (LUTs) and logic registers;
Stratix III devices use combinational adaptive look-up tables (ALUTs) and logic
registers.
Cyclone III Devices
complex multiplier structure, for width 16, for Cyclone III (EP3C10F256C6) devices.
Table 1–3. Performance with the Streaming Data Flow Engine Architecture—Cyclone III Devices
Points
256
1024
Combinational
LUTs
3437
3857
Logic
Registers
3906
4650
Memory
(Bits)
39168
155904
Memory
(M9K)
20
20
9×9
Blocks
24
24
f MAX
(MHz)
231
244
Clock
Cycle
Count
256
1024
Transform
Time ( ? s)
1.11
4.19
4096
3719
4734
622848
76
24
234
4096
17.52
(1) EP3C40F780C6 device.
and bit-reversed outputs, for width 16 (32 for floating point), for Cyclone III
(EP3C16F484C6) devices.
FFT MegaCore Function
User Guide
November 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| 10PX2200MEFC10X16 | CAP ALUM 2200UF 10V 20% RADIAL |
| VE-J7L-EZ-F2 | CONVERTER MOD DC/DC 28V 25W |
| 100ZLH68MEFC8X20 | CAP ALUM 68UF 100V 20% RADIAL |
| VE-J7K-EZ-F4 | CONVERTER MOD DC/DC 40V 25W |
| UPA0J681MPD1TD | CAP ALUM 680UF 6.3V 20% RADIAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-FIR | 功能描述:开发软件 FIR Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPRI2CCMFP001 | 制造商:System Level Solutions (SLS) 功能描述:IP CORE, FPGA, I2C CNTLR, FOR CYCLONE, STRATIX, Software Application:IP CORE, In |
| IPR-ILKN/100G | 功能描述:开发软件 Interlaken - 100G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-ILKN/50G | 功能描述:开发软件 Interlaken - 50G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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