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参数资料
型号： IPR-FFT
厂商： Altera
文件页数： 16/70页
文件大小： 0K
描述： IP FFT/IFFT RENEW
标准包装： 1
系列： *
类型： MegaCore
功能： 快速傅里叶变换处理器
许可证： 续用许可证
1–12
Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–18 lists resource usage with buffered burst data flow architecture, using the
4 multipliers/2 adders complex multiplier structure, for data and twiddle width 16,
for Stratix IV (EP4SGX70DF29C2X) devices.
Table 1–17. Resource Usage with Buffered Burst Data Flow Architecture—Stratix IV Devices
Points
256
1024
4096
256
1024
4096
256
1024
4096
Number of
Engines (1)
1
1
1
2
2
2
4
4
4
Combinational
ALUTs
1951
1990
2034
3262
3307
3348
5712
5774
5856
Logic
Registers
3586
3784
3968
5577
5785
5977
9970
10195
10401
Memory
(Bits)
30976
123136
491776
30976
123136
491776
30976
123136
491776
Memory
(M9K)
16
16
60
31
31
60
60
60
60
18 × 18
Blocks
12
12
12
24
24
24
48
48
48
f MAX
(MHz)
443
441
421
428
410
393
368
362
368
Notes to Table 1–18 :
(1) When using the buffered burst architecture, you can specify the number of quad-output FFT engines in the FFT parameter editor.
Table 1–19 lists performance with buffered burst data flow architecture, using the
4 multipliers/2 adders complex multiplier structure, for data and twiddle width 16,
for Stratix IV (EP4SGX70DF29C2X) devices.
Table 1–18. Performance with the Buffered Burst Data Flow Architecture—Stratix IV Devices
Transform Calculation
Data Load & Transform
Block Throughput
Points
Number of
Engines (1)
f MAX (MHz)
Time (2)
Cycles Time ( ? s)
Calculation
Cycles Time ( ? s)
Cycles
(3)
Time ( ? s)
256
1024
4096
256
1024
4096
256
1024
4096
1
1
1
2
2
2
4
4
4
443
441
421
428
410
393
368
362
368
235
1069
5167
162
557
2607
118
340
1378
0.53
2.42
12.26
0.38
1.36
6.64
0.32
0.94
3.75
491
2093
9263
397
1581
6703
347
1364
5474
1.11
4.75
21.98
0.93
3.85
17.07
0.94
3.77
14.89
331
1291
6157
299
1163
5133
283
1099
4633
0.75
2.93
14.61
0.7
2.84
13.07
0.77
3.04
12.61
Notes to Table 1–19 :
(1) When using the buffered burst architecture, you can specify the number of quad-output engines in the FFT parameter editor. You may choose
from one, two, or four quad-output engines in parallel.
(2) In a buffered burst data flow architecture, transform time is defined as the time from when the N-sample input block is loaded until the first
output sample is ready for output. Transform time does not include the additional N-1 clock cycle to unload the full output data block.
(3) Block throughput is the minimum number of cycles between two successive start-of-packet (sink_sop) pulses.
FFT MegaCore Function
User Guide
November 2013 Altera Corporation
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