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| 型号： | IPR-FFT |
| 厂商： | Altera |
| 文件页数： | 15/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 续用许可证 |
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Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–14. Performance with the Burst Data Flow Architecture—Stratix III Devices (Part 2 of 2)
1–11
Calculation Time
Points
Engine
Architecture
Number of
Engines
(1)
f max
(MHz)
Transform
(2)
Cycles Time ( ? s)
Data Load &
Transform Calculation
Cycles Time ( ? s)
Block Throughput
(3)
Cycles Time ( ? s)
4096
Single Output
2
406
12329
30.34
16495
40.59
20605
50.71
(1) In the burst I/O data flow architecture, you can specify the number of engines in the FFT parameter editor. You may choose from one to two
single-output engines in parallel, or from one, two, or four quad-output engines in parallel.
(2) Transform time is the time frame when the input block is loaded until the first output sample (corresponding to the input block) is output.
Transform time does not include the time to unload the full output data block.
(3) Block throughput is defined as the minimum number of cycles between two successive start-of-packet ( sink_sop ) pulses.
Stratix IV Devices
complex multiplier structure, for data and twiddle width 16, for Stratix IV
(EP4SGX70DF29C2X) devices.
Table 1–15. Performance with the Streaming Data Flow Engine Architecture—Stratix IV Devices
Points
256
1024
4096
Combinational
ALUTs
2092
2480
2356
Logic
Registers
3714
4458
4545
Memory
(Bits)
39,68
155904
622848
Memory
(M9K)
20
20
76
18 × 18
Blocks
12
12
12
f MAX
(MHz)
436
437
419
Clock
Cycle
Count
256
1024
4096
Transform
Time ( ? s)
0.59
2.34
9.78
and bit-reversed outputs, for width 16 (32 for floating point), for Stratix IV
(EP4SGX70DF29C2X) devices.
1
The variable streaming with fixed-point number representation uses natural word
growth, therefore the multiplier requirement is larger compared with the equivalent
streaming FFT with the same number of points.
If you want to significantly reduce M9K memory utilization, set a lower f MAX target.
Table 1–16. Performance with the Variable Streaming Data Flow Engine Architecture—Stratix IV Devices
Point Type
Points
Combinational
ALUTs
Logic
Registers
Memory
Bits M9K
18 × 18
Blocks
f MAX
(MHz)
Clock
Cycle
Count
Transform
Time ( ? s)
Fixed
Fixed
Fixed
Floating
Floating
Floating
256
1024
4096
256
1024
4096
2517
3489
4503
18024
14063
22030
4096
5433
6936
16714
13502
19806
10239
42218
170639
140750
34728
568579
10
15
33
61
89
146
20
28
36
48
64
80
323
329
327
320
314
310
256
1024
4096
256
1024
4096
0.79
3.12
12.52
0.8
3.26
13.23
November 2013
Altera Corporation
FFT MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-FIR | 功能描述:开发软件 FIR Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPRI2CCMFP001 | 制造商:System Level Solutions (SLS) 功能描述:IP CORE, FPGA, I2C CNTLR, FOR CYCLONE, STRATIX, Software Application:IP CORE, In |
| IPR-ILKN/100G | 功能描述:开发软件 Interlaken - 100G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-ILKN/50G | 功能描述:开发软件 Interlaken - 50G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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