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参数资料
| 型号： | IPR-FFT |
| 厂商： | Altera |
| 文件页数： | 44/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 续用许可证 |
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3–2
1
Chapter 3: Functional Description
Variable Streaming Architecture
To maintain a high signal-to-noise ratio throughout the transform computation, the
FFT MegaCore function uses a block-floating-point architecture, which is a trade-off
point between fixed-point and full-floating point architectures.
In a fixed-point architecture, the data precision needs to be large enough to
adequately represent all intermediate values throughout the transform computation.
For large FFT transform sizes, an FFT fixed-point implementation that allows for
word growth can make either the data width excessive or can lead to a loss of
precision.
In a floating-point architecture each number is represented as a mantissa with an
individual exponent—while this leads to greatly improved precision, floating-point
operations tend to demand increased device resources.
In a block-floating point architecture, all of the values have an independent mantissa
but share a common exponent in each data block. Data is input to the FFT function as
fixed point complex numbers (even though the exponent is effectively 0, you do not
enter an exponent).
The block-floating point architecture ensures full use of the data width within the FFT
function and throughout the transform. After every pass through a radix-4 FFT, the
data width may grow up to log 2 (4 ? 2) = 2.5 bits. The data is scaled according to a
measure of the block dynamic range on the output of the previous pass. The number
of shifts is accumulated and then output as an exponent for the entire block. This
shifting ensures that the minimum of least significant bits (LSBs) are discarded prior
to the rounding of the post-multiplication output. In effect, the block-floating point
representation acts as a digital automatic gain control. To yield uniform scaling across
successive output blocks, you must scale the FFT function output by the final
exponent.
In comparing the block-floating point output of the Altera FFT MegaCore function to
the output of a full precision FFT from a tool like MATLAB, you must scale the output
by 2 ( –exponent_ou t ) to account for the discarded LSBs during the transform. (Refer to
Variable Streaming Architecture
The variable streaming architecture uses two different types of architecture,
depending on whether you select the fixed-point data representation or the floating
point representation. If you select the fixed-point data representation, the FFT
variation uses a radix 2 2 single delay feedback architecture, which is a fully pipelined
architecture. If you select the floating point representation, the FFT variation uses a
mixed radix-4/2 architecture. For a length N transform, log 4 ( N ) stages are
concatenated together. The radix 2 2 algorithm has the same multiplicative complexity
of a fully pipelined radix-4 architecture, but the butterfly unit retains a radix-2
architecture. In the radix-4/2 algorithm, a combination of radix-4 and radix-2
architectures are implemented to achieve the computational advantage of the radix-4
architecture while supporting FFT computation with a wider range of transform
lengths. The butterfly units use the DIF decomposition.
FFT MegaCore Function
User Guide
November 2013 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-FIR | 功能描述:开发软件 FIR Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPRI2CCMFP001 | 制造商:System Level Solutions (SLS) 功能描述:IP CORE, FPGA, I2C CNTLR, FOR CYCLONE, STRATIX, Software Application:IP CORE, In |
| IPR-ILKN/100G | 功能描述:开发软件 Interlaken - 100G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-ILKN/50G | 功能描述:开发软件 Interlaken - 50G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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