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型号： IPR-FFT
厂商： Altera
文件页数： 21/70页
文件大小： 0K
描述： IP FFT/IFFT RENEW
标准包装： 1
系列： *
类型： MegaCore
功能： 快速傅里叶变换处理器
许可证： 续用许可证
Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–25. Resource Usage with the Burst Data Flow Architecture—Stratix V Devices
(Part 2 of 2)
1–17
Points
4096
Engine
Architecture
Single Output
Number of
Engines (2)
2
Combinational
ALUTs
1,093
Logic
Registers
2,700
Memory
(Bits)
229,632
Memory
(M20K)
14
DSP
Blocks
4
f MAX
(MHz)
366
Notes to Table 1–20 :
(1) Represents data and twiddle factor precision.
(2) When using the burst data flow architecture, you can specify the number of engines in the FFT parameter editor. You may choose from one to
two single-output engines in parallel, or from one, two, or four quad-output engines in parallel.
Table 1–27 lists performance with burst data flow architecture, using the
4 multipliers/2 adders complex multiplier structure, for data and twiddle width 16,
for Stratix V (5SGXEA7H3F35C2) devices.
Table 1–26. Performance with the Burst Data Flow Architecture—Stratix V Devices
Transform
Data Load & Transform
Block Throughput
Calculation Time
Points
Engine
Architecture
Number of
Engines (1)
f MAX
(MHz)
(2)
Cycles Time ( ? s)
Calculation
Cycles Time ( ? s)
Cycles
(3)
Time ( ? s)
256
1024
4096
256
1024
4096
256
1024
4096
256
1024
4096
256
1024
4096
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Single Output
Single Output
Single Output
Single Output
Single Output
Single Output
1
1
1
2
2
2
4
4
4
1
1
1
2
2
2
414
405
395
385
395
374
353
314
346
445
443
427
401
443
366
235
1,069
5,167
162
557
2,607
118
340
1,378
1,115
5,230
24,705
585
2,652
12,239
0.57
2.64
13.08
0.42
1.41
6.98
0.33
1.08
3.99
2.51
11.79
57.86
1.46
5.99
33.67
491
2,093
9,263
397
1,581
6,703
374
1,364
5,474
1,371
6,344
28,801
841
3,676
16,495
1.18
5.17
23.44
1.03
4
17.94
1.06
4.35
15.84
3.08
14.31
67.45
2.1
8.3
45.05
331
1,291
6,157
299
1,163
5,133
283
1,099
4,633
1,628
7,279
32,898
1,098
4,701
20,605
0.8
3.19
15.58
0.78
2.94
13.74
0.8
3.5
13.4
3.66
16.41
77.05
2.74
10.61
56.27
Notes to Table 1–27 :
(1) In the burst I/O data flow architecture, you can specify the number of engines in the FFT parameter editor. You may choose from one to two
single-output engines in parallel, or from one, two, or four quad-output engines in parallel.
(2) Transform time is the time frame when the input block is loaded until the first output sample (corresponding to the input block) is output.
Transform time does not include the time to unload the full output data block.
(3) Block throughput is defined as the minimum number of cycles between two successive start-of-packet ( sink_sop ) pulses.
November 2013
Altera Corporation
FFT MegaCore Function
User Guide
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