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| 型号： | IPR-FFT |
| 厂商： | Altera |
| 文件页数： | 47/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 续用许可证 |
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Chapter 3: Functional Description
3–5
FFT Processor Engine Architectures
3. The next 8 clock cycles feed the higher order calculations stored in the delay
feedback unit unmodified through the butterfly unit to the next stage.
Subsequent data stages use the same principles. However, the delays in the feedback
path are adjusted accordingly.
Mixed Radix-4/2 Architecture
Mixed radix-4/2 architecture combines the advantages of using radix-2 and radix-4
butterflies.
The architecture has ceiling(log 4 (N)) stages. If transform length is an integral power
of four, all of the log 4 (N) stages are implemented using a radix-4 architecture. If
transform length is not an integral power of four, the architecture implements
ceiling(log 4 (N)) – 1 of the stages in a radix-4 architecture, and implements the
remaining stage using a radix-2 architecture.
Each stage contains a single butterfly unit and a feedback delay unit. The feedback
delay unit delays the incoming data by a specified number of cycles; in each stage the
number of cycles of delay is one quarter of the number of cycles of delay in the
previous stage. The delays align the butterfly input samples correctly for the butterfly
calculations. The output of the pipeline is in index-reversed order.
Quad-Output FFT Engine Architecture
For applications in which transform time is to be minimized, a quad-output FFT
engine architecture is optimal. The term quad-output refers to the throughput of the
internal FFT butterfly processor. The engine implementation computes all four radix-4
butterfly complex outputs in a single clock cycle.
Figure 3–1. Quad-Output FFT Engine
SW
SW
RAM
x[k,0]
G[k,0]
FFT Engine
H[k,0]
BFPU
RAM
A0
A0
RAM
A1
RAM
A2
RAM
A3
x[k,1]
x[k,2]
x[k,3]
-j
-1
-1
j
-1
-j
j
-1
G[k,1]
G[k,2]
G[k,3]
H[k,1]
H[k,2]
H[k,3]
BFPU
BFPU
BFPU
RAM
A1
RAM
A2
RAM
A3
ROM
0
ROM
1
ROM
2
November 2013
Altera Corporation
FFT MegaCore Function
User Guide
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| 100ZLH68MEFC8X20 | CAP ALUM 68UF 100V 20% RADIAL |
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| IPR-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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| IPR-ILKN/50G | 功能描述:开发软件 Interlaken - 50G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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