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参数资料
| 型号： | IPR-FFT |
| 厂商： | Altera |
| 文件页数： | 54/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 续用许可证 |
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3–12
Chapter 3: Functional Description
I/O Data Flow Architectures
When the input block is loaded, the FFT function begins computing the transform on
the stored input block. The sink_ready signal is held high as you can transfer the first
few samples of the subsequent frame into the small FIFO at the input. If this FIFO is
filled, the core deasserts the sink_ready signal. It is not mandatory to transfer samples
during sink_ready cycles. Figure 3–12 shows the input flow control.
Figure 3–12. FFT Buffered Burst Data Flow Architecture Input Flow Control
clk
reset_n
sink_valid
sink_ready
sink_sop
inverse
sink_real
sink_imag
xr(0)
xi(0)
xr(1)
xi(1)
xr(2)
xi(2)
xr(3)
xi(3)
xr(4)
xi(4)
xr(5)
xi(5)
xr(6)
xi(6)
xr(7)
xi(7)
xr(8)
xi(8)
xr(9)
xi(9)
Following the interval of time where the FFT processor reads the input samples from
an internal input buffer, it re-asserts sink_ready indicating it is ready to read in the
next input block. The beginning of the subsequent input block must be demarcated by
the application of a pulse on sink_sop aligned in time with the first input sample of
the next block.
As in all data flow architectures, the logical level of inverse for a particular block is
registered by the FFT function at the time of the assertion of the start-of-packet signal,
sink_sop .
When the FFT has completed the transform of the input block, it asserts the
source_valid and outputs the complex transform domain data block in natural order
Figure 3–13. FFT Buffered Burst Data Flow Architecture Output Flow Control
clk
source_realt
source_imag
Xr[0]
Xi[0]
Xr[1]
Xi[1]
Xr[2]
Xi[2]
Xr[3]
Xi[3]
Xr[4]
Xi[4]
Xr[5]
Xi[5]
Xr[6]
Xi[6]
Xr[7]
Xi[7]
Xr[8]
Xi[8]
Xr[9]
Xi[9]
Xr[10]
Xi[10]
source_exp
EXP0
source_ready
master_source_valid
source_sop
source_eop
Signals source_sop and source_eop indicate the start-of-packet and end-of-packet for
the output block data respectively ( Figure 3–11 ).
1
The sink_valid signal must be asserted for source_valid to be asserted (and a valid
data output). You must therefore leave sink_valid signal asserted at the end of data
transfers to extract the final frames of data from the FFT.
FFT MegaCore Function
User Guide
November 2013 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-FIR | 功能描述:开发软件 FIR Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPRI2CCMFP001 | 制造商:System Level Solutions (SLS) 功能描述:IP CORE, FPGA, I2C CNTLR, FOR CYCLONE, STRATIX, Software Application:IP CORE, In |
| IPR-ILKN/100G | 功能描述:开发软件 Interlaken - 100G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-ILKN/50G | 功能描述:开发软件 Interlaken - 50G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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