- 您现在的位置：买卖IC网 > PDF目录16073 > IPR-FFT (Altera)IP FFT/IFFT RENEW PDF资料下载
参数资料
| 型号： | IPR-FFT |
| 厂商： | Altera |
| 文件页数： | 63/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 续用许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页当前第63页第64页第65页第66页第67页第68页第69页第70页
Appendix A: Block Floating Point Scaling
A–3
Implementing Scaling
A sample of Verilog HDL code that illustrates the scaling of the output data (for
exponents –11 to –9) with sign extension is shown in the following example:
case (exp)
6'b110101 : //-11 Set data equal to MSBs
begin
full_range_real_out[26:0] <= {real_in[15:0],11'b0};
full_range_imag_out[26:0] <= {imag_in[15:0],11'b0};
end
6'b110110 : //-10 Equals left shift by 10 with sign extension
begin
full_range_real_out[26] <= {real_in[15]};
full_range_real_out[25:0] <= {real_in[15:0],10'b0};
full_range_imag_out[26] <= {imag_in[15]};
full_range_imag_out[25:0] <= {imag_in[15:0],10'b0};
end
6'b110111 : //-9 Equals left shift by 9 with sign extension
begin
full_range_real_out[26:25] <= {real_in[15],real_in[15]};
full_range_real_out[24:0] <= {real_in[15:0],9'b0};
full_range_imag_out[26:25] <= {imag_in[15],imag_in[15]};
full_range_imag_out[24:0] <= {imag_in[15:0],9'b0};
end
.
.
.
endcase
In this example, the output provides a full scale 27-bit word. You must choose how
many and which bits must be carried forward in the processing chain. The choice of
bits determines the absolute gain relative to the input sample level.
the 256-point quad output FFT with an input signal level of 0x5000. The output of the
FFT is 0x280 when the exponent = –5. The figure illustrates all cases of valid exponent
values of scaling to the full scale storage register [26..0]. Because the exponent is –5,
you must check the register values for that column. This data is shown in the last two
columns in the figure. Note that the last column represents the gain compensated data
after the scaling (0x0005000), which agrees with the input data as expected. If you
want to keep 16 bits for subsequent processing, you can choose the bottom 16 bits that
result in 0x5000. However, if you choose a different bit range, such as the top 16 bits,
the result is 0x000A. Therefore, the choice of bits affects the relative gain through the
processing chain.
November 2013
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| 10PX2200MEFC10X16 | CAP ALUM 2200UF 10V 20% RADIAL |
| VE-J7L-EZ-F2 | CONVERTER MOD DC/DC 28V 25W |
| 100ZLH68MEFC8X20 | CAP ALUM 68UF 100V 20% RADIAL |
| VE-J7K-EZ-F4 | CONVERTER MOD DC/DC 40V 25W |
| UPA0J681MPD1TD | CAP ALUM 680UF 6.3V 20% RADIAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-FIR | 功能描述:开发软件 FIR Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPRI2CCMFP001 | 制造商:System Level Solutions (SLS) 功能描述:IP CORE, FPGA, I2C CNTLR, FOR CYCLONE, STRATIX, Software Application:IP CORE, In |
| IPR-ILKN/100G | 功能描述:开发软件 Interlaken - 100G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-ILKN/50G | 功能描述:开发软件 Interlaken - 50G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。