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| 型号： | IPR-FFT |
| 厂商： | Altera |
| 文件页数： | 31/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 续用许可证 |
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Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
1
2–7
A single FFT engine architecture provides enough performance for up to a
1,024-point streaming I/O data flow FFT.
If you select Variable Streaming I/O data flow, the Transform length (specified
on the Parameters Tab) represents the maximum transform length that can be
performed. You can perform all transforms of length 2 m where 6 ? m ?
log 2 ( transform length ) at runtime. Floating-point bidirectional IP cores expect input
in natural order for forward transforms and digit reverse order for reverse
transforms. The output order is digit reverse order for forward transforms and
natural order for reverse transforms.
1
If you select Variable Streaming and Floating Point on the Architecture
tab, the precision (on the Parameters tab) is automatically set to 32, and the
reverse I/O order options (on the Architecture tab) are Digit Reverse
Order .
If you select Variable Streaming I/O data flow, options to set the I/O order and
data representation are visible. The Input Order option allow you to select the
order in which the samples are presented to the FFT. If you select Natural Order ,
the FFT expects the order of the input samples to be sequential (1, 2 …, n – 1, n )
where n is the size of the current transform. For Bit Reverse Order , the FFT expects
the input samples to be in bit-reversed order. For Digit Reverse Order , the FFT
expects the input samples to be in digit-reversed order. For –N/2 to N/2 , the FFT
expects the input samples to be in the order – N /2 to ( N /2) – 1 (also known as DC-
centered order). Similarly the Output Order option specifies the order in which
the FFT generates the output. Whether you can select Bit Reverse Order or Digit
Reverse Order depends on your Data Representation selection. You can select
Fixed Point or Floating Point data representation. If you select Fixed Point , the
FFT variation implements the radix-2 2 architecture and the reverse I/O order
option is Bit Reverse Order ; if you select Floating Point , the FFT variation
implements the mixed radix-4/2 architecture and the reverse I/O order option is
Digit Reverse Order .
For sample digit-reversed order, if n is a power of four, the order is radix-4
digit-reversed order, in which two-bit digits in the sample number are units in the
reverse ordering. For example, if n = 16, sample number 4 becomes the second
sample in the sample stream (by reversal of the digits in 0001, the location in the
sample stream, to 0100). However, in mixed radix-4/2 architecture, n need not be a
power of four. If n is not a power of four, the two-bit digits are grouped from the
least significant bit, and the most significant bit becomes the least significant bit in
the digit-reversed order. For example, if n = 32, the sample number 18 (10010) in
the natural ordering becomes sample number 17 (10001) in the digit-reversed
order.
November 2013
Altera Corporation
FFT MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-FIR | 功能描述:开发软件 FIR Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPRI2CCMFP001 | 制造商:System Level Solutions (SLS) 功能描述:IP CORE, FPGA, I2C CNTLR, FOR CYCLONE, STRATIX, Software Application:IP CORE, In |
| IPR-ILKN/100G | 功能描述:开发软件 Interlaken - 100G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-ILKN/50G | 功能描述:开发软件 Interlaken - 50G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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