收藏本站
参数资料
型号： IPR-FFT
厂商： Altera
文件页数： 20/70页
文件大小： 0K
描述： IP FFT/IFFT RENEW
标准包装： 1
系列： *
类型： MegaCore
功能： 快速傅里叶变换处理器
许可证： 续用许可证
1–16
Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–25 lists performance with buffered burst data flow architecture, using the
4 multipliers/2 adders complex multiplier structure, for data and twiddle width 16,
for Stratix V (5SGXEA7H3F35C2) devices.
Table 1–24. Performance with the Buffered Burst Data Flow Architecture—Stratix V Devices
Transform Calculation
Data Load & Transform
Block Throughput
Points
Number of
Engines (1)
f MAX (MHz)
Time (2)
Cycles Time ( ? s)
Calculation
Cycles Time ( ? s)
Cycles
(3)
Time ( ? s)
256
1024
4096
256
1024
4096
256
1024
4096
1
1
1
2
2
2
4
4
4
430
403
402
380
379
366
337
348
312
235
1,069
5,167
162
557
2,607
118
340
1,378
0.55
2.65
12.86
0.43
1.47
7.13
0.35
0.98
4.42
491
2,093
9,263
397
1,581
6,703
347
1,364
5,474
1.14
5.19
23.06
1.05
4.17
18.33
1.03
3.92
17.54
331
1,291
6,157
299
1,163
5,133
283
1,099
4,633
0.77
3.2
15.32
0.79
3.07
14.04
0.84
3.16
14.84
Notes to Table 1–25 :
(1) When using the buffered burst architecture, you can specify the number of quad-output engines in the FFT parameter editor. You may choose
from one, two, or four quad-output engines in parallel.
(2) In a buffered burst data flow architecture, transform time is defined as the time from when the N-sample input block is loaded until the first
output sample is ready for output. Transform time does not include the additional N-1 clock cycle to unload the full output data block.
(3) Block throughput is the minimum number of cycles between two successive start-of-packet (sink_sop) pulses.
Table 1–26 lists resource usage with burst data flow architecture, using the
4 multipliers/2 adders complex multiplier structure, for data and twiddle width 16,
for Stratix V (5SGXEA7H3F35C2) devices.
Table 1–25. Resource Usage with the Burst Data Flow Architecture—Stratix V Devices
(Part 1 of 2)
Points
256
1024
4096
256
1024
4096
256
1024
4096
256
1024
4096
256
1024
Engine
Architecture
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Quad Output
Single Output
Single Output
Single Output
Single Output
Single Output
Number of
Engines (2)
1
1
1
2
2
2
4
4
4
1
1
1
2
2
Combinational
ALUTs
1,801
1,833
1,878
2,970
3,019
3,048
5,164
5,216
5,280
709
751
817
1,037
1,052
Logic
Registers
3,717
3,912
4,078
5,914
6,129
6,319
10,743
10,924
11,129
1,542
1,598
1,637
2,521
2,622
Memory
(Bits)
14,592
57,600
229,632
14,592
57,600
229,632
14,592
57,600
229,632
9,472
37,120
147,712
14,592
57,600
Memory
(M20K)
8
8
14
14
14
14
27
27
27
3
4
9
8
8
DSP
Blocks
6
6
6
12
12
12
24
24
24
2
2
2
4
4
f MAX
(MHz)
414
405
395
385
395
374
353
314
346
445
443
427
401
443
FFT MegaCore Function
User Guide
November 2013 Altera Corporation
相关PDF资料
PDF描述
10PX2200MEFC10X16 CAP ALUM 2200UF 10V 20% RADIAL
VE-J7L-EZ-F2 CONVERTER MOD DC/DC 28V 25W
100ZLH68MEFC8X20 CAP ALUM 68UF 100V 20% RADIAL
VE-J7K-EZ-F4 CONVERTER MOD DC/DC 40V 25W
UPA0J681MPD1TD CAP ALUM 680UF 6.3V 20% RADIAL
相关代理商/技术参数
参数描述
IPR-FIR 功能描述:开发软件 FIR Compiler MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-FIRII 功能描述:开发软件 FIR Compiler II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPRI2CCMFP001 制造商:System Level Solutions (SLS) 功能描述:IP CORE, FPGA, I2C CNTLR, FOR CYCLONE, STRATIX, Software Application:IP CORE, In
IPR-ILKN/100G 功能描述:开发软件 Interlaken - 100G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-ILKN/50G 功能描述:开发软件 Interlaken - 50G MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*