参数资料
型号: MC92603VF
厂商: Freescale Semiconductor
文件页数: 118/126页
文件大小: 0K
描述: IC TXRX ETH QUAD GIG 256-MAPBGA
标准包装: 1
类型: 收发器
驱动器/接收器数: 4/4
规程: 千兆位以太网
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-MAPBGA
包装: 托盘
Electrical Specifications and Characteristics
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
7-9
7.3.2.2
Receiver Interface, DDR Timing
The following sections provides the receiver, DDR timing specifications for the MC92603.
7.3.2.2.1
Receiver, DDR Clock Timing (All Modes Except Ethernet RTBI Modes)
Figure 7-5 provides the receiver interface DDR timing diagram when TBIE is negated low or COMPAT is
negated low.
Figure 7-5. Receiver, DDR Timing Diagram (TBIE = Low or COMPAT = Low)
Table 7-9 provides the receiver, DDR timing specifications when TBIE is negated low or COMPAT is
negated low.
Table 7-9. Receiver, DDR Timing Specification (TBIE = Low or COMPAT = Low)
Symbol
Characteristic 1
1 10 pF output load.
Aligned Clock
Centered Clock
Unit
Note
Min
Max
Min
Max
T1
Output valid time before rising/falling edge of
RECV_x_RCLK
–0.500
0.500
1.440
ns
2
2 Full speed, HSE = low.
–1.000
1.000
3.440
ns
3
3 Half speed, HSE = high.
T2
Output valid time after rising/falling edge of
RECV_x_RCLK
3.000
1.420
ns
7.000
3.500
ns
T3
RECV_x_RCLK cycle time
7.800
8.200
7.800
8.200
ns
15.800
16.200
15.800
16.200
ns
T4
RECV_x_RCLK half-cycle time
3.800
4.200
3.800
4.200
ns
7.800
8.200
7.800
8.200
ns
T1
T2
RECV_x_3–0
RECV_x_ERR
RECV_x_DV
RECV_x_COMMA
T1
T2
RECV_x_RCLK
T3
T4
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