- 您现在的位置：买卖IC网 > PDF目录2012 > MC92603VF (Freescale Semiconductor)IC TXRX ETH QUAD GIG 256-MAPBGA PDF资料下载
参数资料
| 型号： | MC92603VF |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 74/126页 |
| 文件大小： | 0K |
| 描述： | IC TXRX ETH QUAD GIG 256-MAPBGA |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 4/4 |
| 规程： | 千兆位以太网 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-MAPBGA |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页当前第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页
Receiver
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
3-17
3.7.2
Rate Adaption of Ethernet Packet Data Streams
The MC92603 supports applications in which the device is used to transmit and receive IEEE Std.
802.3-2002, PCS, PMA, type 1000BASE-X packet streams. When the MC92603 is being operated in
reference clock mode, as described in Section 3.6.2, “Reference Clock Timing Mode (RCCE = Low),” rate
adaption is performed to account for frequency offset between the transmitter and receiver. In backplane
applications (see Section 3.6.2, “Reference Clock Timing Mode (RCCE = Low)”), rate adaption is
accommodated by adding K28.5 IDLE code groups to, or deleting K28.5 IDLE code groups from, the data
stream to match the incoming data rate to the receiver data rate as defined by its reference clock frequency.
The indiscriminate addition or deletion of K28.5 IDLE code groups from an 802.3 packet stream would
interfere with proper system operation.
The MC92603 compatibility mode (COMPAT input is high) allows for rate adaption using methods
compatible with Ethernet packet streams and does not interfere with proper system operation. The
following are the features of the compatibility mode:
Context-sensitive rate adaption during receipt of configuration, IDLE, and data code groups
Tolerates up to +100 ppm frequency offset
Supports Jumbo frame lengths of up to 14 Kbytes (if JPACK is high)
Supports frame bursting
Internal or external 8B/10B encoding/decoding may be used
Compatible with IEEE Std. 802.3-2002 Clause 4 specification [4] of media access control function
Compatible with Clause 36 of the specification [4] of physical coding sublayer (PCS) and physical
medium attachment (PMA) sublayer function
Compatible with Clause 37 of the specification [4] of auto-negotiation function
3.7.2.1
Rate Adaption Method
The MC92603 utilizes a FIFO in its receiver to act as an elastic buffer for the receive data interface. The
elastic buffer allows for proper operation of the interface in the presence of jitter and frequency offset.
However, frequency offset will eventually lead to elastic buffer overrun or underrun. In order to prevent
underruns and overruns, one or more code groups must be added to or deleted from the packet stream.
The MC92603 must determine the proper type of code groups to add or delete and do it at an appropriate
time to ensure compatibility with the packet data streams. The code group type and timing is determined
by the current context of the packet stream. There are three contexts considered: configuration, idle, and
data transmission.
3.7.2.2
Configuration Context
The configuration context is when the transceivers are transmitting configuration ordered sets in support
of auto-negotiation. A configuration ordered set consists of alternating /C1/ and /C2/ code group sets as
shown below:
/C1/: /K28.5/D21.5/Dxx.x/Dxx.x
/C2/: /K28.5/D2.2/Dxx.x/Dxx.x
相关PDF资料 |
PDF描述 |
|---|---|
| MC92604VM | IC ETH TXRX DUAL GIG 196-MAPBGA |
| MC92604ZT | IC TXRX ETH DUAL GIG 196-MAPBGA |
| MCP2120T-I/SL | IC ENCODR/DECODR 2.5V IR 14-SOIC |
| MCP2122-E/P | IC ENCODER/DECODER IRDA 8-DIP |
| MCP2122T-E/SNG | IC ENCODER/DECODR INFRARED 8SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC92603VM | 功能描述:IC ETH TXRX QUAD GIG 256-MAPBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| MC92604VM | 功能描述:IC ETH TXRX DUAL GIG 196-MAPBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| MC92604ZT | 功能描述:IC TXRX ETH DUAL GIG 196-MAPBGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
| MC92610 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Quad 3.125 Gbaud SERDES |
| MC92610VF | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Quad 3.125 Gbaud SERDES |
发布紧急采购，3分钟左右您将得到回复。